Operation set customization in retargetable compilers
Research output: Scientific - peer-review › Conference contribution
Details
| Original language | English |
|---|---|
| Title of host publication | Signals, Systems and Computers ASILOMAR, 2011 Conference Record of the Forty Fifth Asilomar Conference, 6-9 November 2011, Pacific Grove, CA, United States |
| Publisher | IEEE Computer Society |
| Pages | 761-765 |
| ISBN (Print) | 978-1-4673-0321-7 |
| DOIs | |
| State | Published - 2011 |
| Publication type | A4 Article in a conference publication |
| Event | Asilomar Conference on Signals, Systems and Computers - |
Publication series
| Name | Asilomar Conference on Signals, Systems and Computers |
|---|---|
| Publisher | IEEE Computer Society |
| ISSN (Print) | 1058-6393 |
Conference
| Conference | Asilomar Conference on Signals, Systems and Computers |
|---|---|
| Period | 1/01/00 → … |
Abstract
The core tool in Application-Specific Instruction Set Processor (ASIP) design toolsets is a retargetable compiler, which can generate efficient code to any processor developed with the toolset. Such a compiler must automatically adapt itself to the operation set supported by the designed processor by emulating missing instructions with other instructions and by selecting custom instructions automatically whenever possible. This paper proposes a simplified Directed Acyclic Graph-based recursive mechanism to support operation set customization. The proposed mechanism is capable of generating instruction selectors and architecture simulation models automatically, thus is suitable for fast design space exploration of ASIP operation sets.
Publication forum classification
Field of science, Statistics Finland
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