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Parallel memory architecture for arbitrary stride accesses

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationProceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 18-21 April, 2006, Prague, Czech Republic
EditorsM.S. Reorda
Pages65-70
Publication statusPublished - 2006
Publication typeA4 Article in a conference publication

Publication forum classification