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Partial expansion of dataflow graphs for resource-aware scheduling of multicore signal processing systems

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationConference Record of the 48th Asilomar Conference on Signals, Systems and Computers
PublisherIEEE COMPUTER SOCIETY PRESS
Pages385-392
Number of pages8
Volume2015-April
ISBN (Electronic)9781479982974
DOIs
Publication statusPublished - 24 Apr 2015
Publication typeA4 Article in a conference publication
Event48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 - Pacific Grove, United States
Duration: 2 Nov 20145 Nov 2014

Conference

Conference48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015
CountryUnited States
CityPacific Grove
Period2/11/145/11/14

Abstract

The complex design spaces associated with state-of-the-art, multicore signal processing systems pose significant challenges in realizing designs with high productivity and quality. The Partial Expansion Graph (PEG) implementation model was developed to help address these challenges by enabling more efficient exploration of the scheduling design space for multicore digital signal processors. The PEG allows designers and design tools to systematically adjust and adapt the amount of parallelism exposed from applications depending on the targeted platform. In this paper, we develop new algorithms for scheduling and mapping systems implemented using PEGs. Collectively, these algorithms operate in three steps. First, the amount of data parallelism in the application graph is tuned systematically over many iterations to profit from the available cores in the target platform. Then a mapping algorithm that uses graph analysis is developed to distribute data and task parallel instances over different cores while trying to balance the load of all processing units to make use of pipeline parallelism. Finally, we use a novel technique for performance evaluation by implementing the scheduler and a customizable solution on the programmable platform. We demonstrate the utility of our PEG-based scheduling and mapping algorithms through experiments on real application models and various synthetic graphs.

Keywords

  • Dataflow Graphs, Digital Signal Processing, Dynamic Scheduling, Multiprocessor Scheduling