Tampere University of Technology

TUTCRIS Research Portal

Plasma etch technologies for the development of ultra-small feature size transistor devices

Research output: Contribution to journalArticleScientificpeer-review

Details

Original languageEnglish
Article number174012
JournalJournal of Physics D: Applied Physics
Volume44
Issue number17
DOIs
Publication statusPublished - 4 May 2011
Publication typeA1 Journal article-refereed

Abstract

The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is 'transferred' to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.