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Plasma etch technologies for the development of ultra-small feature size transistor devices

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Plasma etch technologies for the development of ultra-small feature size transistor devices. / Borah, D.; Shaw, M. T.; Rasappa, S.; Farrell, R. A.; O'Mahony, C.; Faulkner, C. M.; Bosea, M.; Gleeson, P.; Holmes, J. D.; Morris, M. A.

In: Journal of Physics D: Applied Physics, Vol. 44, No. 17, 174012, 04.05.2011.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Borah, D, Shaw, MT, Rasappa, S, Farrell, RA, O'Mahony, C, Faulkner, CM, Bosea, M, Gleeson, P, Holmes, JD & Morris, MA 2011, 'Plasma etch technologies for the development of ultra-small feature size transistor devices', Journal of Physics D: Applied Physics, vol. 44, no. 17, 174012. https://doi.org/10.1088/0022-3727/44/17/174012

APA

Borah, D., Shaw, M. T., Rasappa, S., Farrell, R. A., O'Mahony, C., Faulkner, C. M., ... Morris, M. A. (2011). Plasma etch technologies for the development of ultra-small feature size transistor devices. Journal of Physics D: Applied Physics, 44(17), [174012]. https://doi.org/10.1088/0022-3727/44/17/174012

Vancouver

Borah D, Shaw MT, Rasappa S, Farrell RA, O'Mahony C, Faulkner CM et al. Plasma etch technologies for the development of ultra-small feature size transistor devices. Journal of Physics D: Applied Physics. 2011 May 4;44(17). 174012. https://doi.org/10.1088/0022-3727/44/17/174012

Author

Borah, D. ; Shaw, M. T. ; Rasappa, S. ; Farrell, R. A. ; O'Mahony, C. ; Faulkner, C. M. ; Bosea, M. ; Gleeson, P. ; Holmes, J. D. ; Morris, M. A. / Plasma etch technologies for the development of ultra-small feature size transistor devices. In: Journal of Physics D: Applied Physics. 2011 ; Vol. 44, No. 17.

Bibtex - Download

@article{7717698b5218418fa6245ba27b2d6bd3,
title = "Plasma etch technologies for the development of ultra-small feature size transistor devices",
abstract = "The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is 'transferred' to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.",
author = "D. Borah and Shaw, {M. T.} and S. Rasappa and Farrell, {R. A.} and C. O'Mahony and Faulkner, {C. M.} and M. Bosea and P. Gleeson and Holmes, {J. D.} and Morris, {M. A.}",
year = "2011",
month = "5",
day = "4",
doi = "10.1088/0022-3727/44/17/174012",
language = "English",
volume = "44",
journal = "Journal of Physics D: Applied Physics",
issn = "0022-3727",
publisher = "IOP Publishing",
number = "17",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Plasma etch technologies for the development of ultra-small feature size transistor devices

AU - Borah, D.

AU - Shaw, M. T.

AU - Rasappa, S.

AU - Farrell, R. A.

AU - O'Mahony, C.

AU - Faulkner, C. M.

AU - Bosea, M.

AU - Gleeson, P.

AU - Holmes, J. D.

AU - Morris, M. A.

PY - 2011/5/4

Y1 - 2011/5/4

N2 - The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is 'transferred' to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.

AB - The advances in information and communication technologies have been largely predicated around the increases in computer processor power derived from the constant miniaturization (and consequent higher density) of individual transistors. Transistor design has been largely unchanged for many years and progress has been around scaling of the basic CMOS device. Scaling has been enabled by photolithography improvements (i.e. patterning) and secondary processing such as deposition, implantation, planarization, etc. Perhaps the most important of the secondary processes is the plasma etch methodology whereby the pattern created by lithography is 'transferred' to the surface via a selective etch to remove exposed material. However, plasma etch technologies face challenges as scaling continues. Maintaining absolute fidelity in pattern transfer at sub-16 nm dimensions will require advances in plasma technology (plasma sources, chamber design, etc) and chemistry (etch gases, flows, interactions with substrates, etc). In this paper, we illustrate some of these challenges by discussing the formation of ultra-small device structures from the directed self-assembly of block copolymers (BCPs) where nanopatterns are formed from the micro-phase separation of the system. The polymer pattern is transferred by a double etch procedure where one block is selectively removed and the remaining block acts as a resist pattern for silicon pattern transfer. Data are presented which shows that highly regular nanowire patterns of feature size below 20 nm can be created using etch optimization techniques and in this paper we demonstrate generation of crystalline silicon nanowire arrays with feature sizes below 8 nm. BCP techniques are demonstrated to be applicable from these ultra-small feature sizes to 40 nm dimensions. Etch profiles show rounding effects because etch selectivity in these nanoscale resist patterns is limited and the resist thickness rather low. The nanoscale nature of the topography generated also places high demands on developing new etch processes.

UR - http://www.scopus.com/inward/record.url?scp=79954607730&partnerID=8YFLogxK

U2 - 10.1088/0022-3727/44/17/174012

DO - 10.1088/0022-3727/44/17/174012

M3 - Article

VL - 44

JO - Journal of Physics D: Applied Physics

JF - Journal of Physics D: Applied Physics

SN - 0022-3727

IS - 17

M1 - 174012

ER -