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Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

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Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture. / Hussain, Waqar; Hoffmann, Henry; Ahonen, Tapani; Nurmi, Jari.

In: Journal of Signal Processing Systems, Vol. 87, No. 3, 06.2017, p. 287–297.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Hussain, W, Hoffmann, H, Ahonen, T & Nurmi, J 2017, 'Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture' Journal of Signal Processing Systems, vol. 87, no. 3, pp. 287–297. https://doi.org/10.1007/s11265-016-1142-5

APA

Hussain, W., Hoffmann, H., Ahonen, T., & Nurmi, J. (2017). Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture. Journal of Signal Processing Systems, 87(3), 287–297. https://doi.org/10.1007/s11265-016-1142-5

Vancouver

Author

Hussain, Waqar ; Hoffmann, Henry ; Ahonen, Tapani ; Nurmi, Jari. / Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture. In: Journal of Signal Processing Systems. 2017 ; Vol. 87, No. 3. pp. 287–297.

Bibtex - Download

@article{a8e79932a8a948b98b56cd0797cabff4,
title = "Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture",
abstract = "This paper presents an integrated self-aware computing model mitigating the power dissipation of a heterogeneous reconfigurable multicore architecture by dynamically scaling the operating frequency of each core. The power mitigation is achieved by equalizing the performance of all the cores for an uninterrupted exchange of data. The multicore platform consists of heterogeneous Coarse-Grained Reconfigurable Arrays (CGRAs) of application-specific sizes and a Reduced Instruction-Set Computing (RISC) core. The CGRAs and the RISC core are integrated with each other over a Network-on-Chip (NoC) of six nodes arranged in a topology of two rows and three columns. The RISC core constantly monitors and controls the performance of each CGRA accelerator by adjusting the operating frequencies unless the performance of all the CGRAs is optimally balanced over the platform. The CGRA cores on the platform are processing some of the most computationally-intensive signal processing algorithms while the RISC core establishes packet based synchronization between the cores for computation and communication. All the cores can access each other’s computational and memory resources while processing the kernels simultaneously and independently of each other. Besides general-purpose processing and overall platform supervision, the RISC processor manages performance equalization among all the cores which mitigates the overall dynamic power dissipation by 20.7 {\%} for a proof-of-concept test.",
keywords = "CGRA, Dark silicon, Heterogeneous, Multicore, Power dissipation, Reconfigurable",
author = "Waqar Hussain and Henry Hoffmann and Tapani Ahonen and Jari Nurmi",
year = "2017",
month = "6",
doi = "10.1007/s11265-016-1142-5",
language = "English",
volume = "87",
pages = "287–297",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer Verlag",
number = "3",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

AU - Hussain, Waqar

AU - Hoffmann, Henry

AU - Ahonen, Tapani

AU - Nurmi, Jari

PY - 2017/6

Y1 - 2017/6

N2 - This paper presents an integrated self-aware computing model mitigating the power dissipation of a heterogeneous reconfigurable multicore architecture by dynamically scaling the operating frequency of each core. The power mitigation is achieved by equalizing the performance of all the cores for an uninterrupted exchange of data. The multicore platform consists of heterogeneous Coarse-Grained Reconfigurable Arrays (CGRAs) of application-specific sizes and a Reduced Instruction-Set Computing (RISC) core. The CGRAs and the RISC core are integrated with each other over a Network-on-Chip (NoC) of six nodes arranged in a topology of two rows and three columns. The RISC core constantly monitors and controls the performance of each CGRA accelerator by adjusting the operating frequencies unless the performance of all the CGRAs is optimally balanced over the platform. The CGRA cores on the platform are processing some of the most computationally-intensive signal processing algorithms while the RISC core establishes packet based synchronization between the cores for computation and communication. All the cores can access each other’s computational and memory resources while processing the kernels simultaneously and independently of each other. Besides general-purpose processing and overall platform supervision, the RISC processor manages performance equalization among all the cores which mitigates the overall dynamic power dissipation by 20.7 % for a proof-of-concept test.

AB - This paper presents an integrated self-aware computing model mitigating the power dissipation of a heterogeneous reconfigurable multicore architecture by dynamically scaling the operating frequency of each core. The power mitigation is achieved by equalizing the performance of all the cores for an uninterrupted exchange of data. The multicore platform consists of heterogeneous Coarse-Grained Reconfigurable Arrays (CGRAs) of application-specific sizes and a Reduced Instruction-Set Computing (RISC) core. The CGRAs and the RISC core are integrated with each other over a Network-on-Chip (NoC) of six nodes arranged in a topology of two rows and three columns. The RISC core constantly monitors and controls the performance of each CGRA accelerator by adjusting the operating frequencies unless the performance of all the CGRAs is optimally balanced over the platform. The CGRA cores on the platform are processing some of the most computationally-intensive signal processing algorithms while the RISC core establishes packet based synchronization between the cores for computation and communication. All the cores can access each other’s computational and memory resources while processing the kernels simultaneously and independently of each other. Besides general-purpose processing and overall platform supervision, the RISC processor manages performance equalization among all the cores which mitigates the overall dynamic power dissipation by 20.7 % for a proof-of-concept test.

KW - CGRA

KW - Dark silicon

KW - Heterogeneous

KW - Multicore

KW - Power dissipation

KW - Reconfigurable

U2 - 10.1007/s11265-016-1142-5

DO - 10.1007/s11265-016-1142-5

M3 - Article

VL - 87

SP - 287

EP - 297

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 3

ER -