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Processor core for 32 kbit/s G.726 ADPCM codecs

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication1995 IEEE International Symposium on Circuits and Systems. ISCAS '95
PublisherIEEE
Pages1932-1935
Number of pages4
Volume3
ISBN (Print)0-7803-2570-2
DOIs
Publication statusPublished - 1995
Publication typeA4 Article in a conference publication
EventProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3) - Seattle, WA, USA
Duration: 30 Apr 19953 May 1995

Conference

ConferenceProceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3)
CitySeattle, WA, USA
Period30/04/953/05/95

Abstract

This paper describes an application specific DSP core designed to be used in a CCITT 32 kbit/s G.726 Adaptive Differential Pulse Code Modulation codec. The instruction set architecture and the programming model of the DSP core were derived from an algorithm profile and complexity analysis and the core was implemented using VHDL and logic synthesis. Architecture design efforts were concentrated on finding the minimum amount of hardware resources which could implement the required functionality within the clock cycle count limit. The result is a Harvard architecture processor core which can be used to implement the 32 kbit/s G.726 ADPCM encoding/decoding functions with very modest external instruction and data memory requirements. In a typical configuration the processor can perform a full encode decode operation for one sample in less than 1100 clock cycles. A gate-level implementation of less than 4000 gates of silicon area was created using logic synthesis for a standard cell technology.