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Processor core for 32 kbit/s G.726 ADPCM codecs

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Standard

Processor core for 32 kbit/s G.726 ADPCM codecs. / Vehviläinen, Juhani; Nurmi, Jari.

1995 IEEE International Symposium on Circuits and Systems. ISCAS '95. Vol. 3 IEEE, 1995. p. 1932-1935.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Vehviläinen, J & Nurmi, J 1995, Processor core for 32 kbit/s G.726 ADPCM codecs. in 1995 IEEE International Symposium on Circuits and Systems. ISCAS '95. vol. 3, IEEE, pp. 1932-1935, Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95. Part 3 (of 3), Seattle, WA, USA, 30/04/95. https://doi.org/10.1109/ISCAS.1995.523797

APA

Vehviläinen, J., & Nurmi, J. (1995). Processor core for 32 kbit/s G.726 ADPCM codecs. In 1995 IEEE International Symposium on Circuits and Systems. ISCAS '95 (Vol. 3, pp. 1932-1935). IEEE. https://doi.org/10.1109/ISCAS.1995.523797

Vancouver

Vehviläinen J, Nurmi J. Processor core for 32 kbit/s G.726 ADPCM codecs. In 1995 IEEE International Symposium on Circuits and Systems. ISCAS '95. Vol. 3. IEEE. 1995. p. 1932-1935 https://doi.org/10.1109/ISCAS.1995.523797

Author

Vehviläinen, Juhani ; Nurmi, Jari. / Processor core for 32 kbit/s G.726 ADPCM codecs. 1995 IEEE International Symposium on Circuits and Systems. ISCAS '95. Vol. 3 IEEE, 1995. pp. 1932-1935

Bibtex - Download

@inproceedings{7f30be25099d4abf9d9f16ddf3032a3b,
title = "Processor core for 32 kbit/s G.726 ADPCM codecs",
abstract = "This paper describes an application specific DSP core designed to be used in a CCITT 32 kbit/s G.726 Adaptive Differential Pulse Code Modulation codec. The instruction set architecture and the programming model of the DSP core were derived from an algorithm profile and complexity analysis and the core was implemented using VHDL and logic synthesis. Architecture design efforts were concentrated on finding the minimum amount of hardware resources which could implement the required functionality within the clock cycle count limit. The result is a Harvard architecture processor core which can be used to implement the 32 kbit/s G.726 ADPCM encoding/decoding functions with very modest external instruction and data memory requirements. In a typical configuration the processor can perform a full encode decode operation for one sample in less than 1100 clock cycles. A gate-level implementation of less than 4000 gates of silicon area was created using logic synthesis for a standard cell technology.",
author = "Juhani Vehvil{\"a}inen and Jari Nurmi",
year = "1995",
doi = "10.1109/ISCAS.1995.523797",
language = "English",
isbn = "0-7803-2570-2",
volume = "3",
pages = "1932--1935",
booktitle = "1995 IEEE International Symposium on Circuits and Systems. ISCAS '95",
publisher = "IEEE",

}

RIS (suitable for import to EndNote) - Download

TY - GEN

T1 - Processor core for 32 kbit/s G.726 ADPCM codecs

AU - Vehviläinen, Juhani

AU - Nurmi, Jari

PY - 1995

Y1 - 1995

N2 - This paper describes an application specific DSP core designed to be used in a CCITT 32 kbit/s G.726 Adaptive Differential Pulse Code Modulation codec. The instruction set architecture and the programming model of the DSP core were derived from an algorithm profile and complexity analysis and the core was implemented using VHDL and logic synthesis. Architecture design efforts were concentrated on finding the minimum amount of hardware resources which could implement the required functionality within the clock cycle count limit. The result is a Harvard architecture processor core which can be used to implement the 32 kbit/s G.726 ADPCM encoding/decoding functions with very modest external instruction and data memory requirements. In a typical configuration the processor can perform a full encode decode operation for one sample in less than 1100 clock cycles. A gate-level implementation of less than 4000 gates of silicon area was created using logic synthesis for a standard cell technology.

AB - This paper describes an application specific DSP core designed to be used in a CCITT 32 kbit/s G.726 Adaptive Differential Pulse Code Modulation codec. The instruction set architecture and the programming model of the DSP core were derived from an algorithm profile and complexity analysis and the core was implemented using VHDL and logic synthesis. Architecture design efforts were concentrated on finding the minimum amount of hardware resources which could implement the required functionality within the clock cycle count limit. The result is a Harvard architecture processor core which can be used to implement the 32 kbit/s G.726 ADPCM encoding/decoding functions with very modest external instruction and data memory requirements. In a typical configuration the processor can perform a full encode decode operation for one sample in less than 1100 clock cycles. A gate-level implementation of less than 4000 gates of silicon area was created using logic synthesis for a standard cell technology.

U2 - 10.1109/ISCAS.1995.523797

DO - 10.1109/ISCAS.1995.523797

M3 - Conference contribution

SN - 0-7803-2570-2

VL - 3

SP - 1932

EP - 1935

BT - 1995 IEEE International Symposium on Circuits and Systems. ISCAS '95

PB - IEEE

ER -