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Programmable and Scalable Architecture for Graphics Processing Units

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Details

Original languageEnglish
Title of host publicationTransactions on High-Performance Embedded Architectures and Compilers V
EditorsPer Stenström, Cristina Silvano, Koen Bertels, Mike Schulte
PublisherSpringer Nature
Pages21-38
ISBN (Electronic)978-3-662-58834-5
ISBN (Print)978-3-662-58833-8
DOIs
Publication statusPublished - 23 Feb 2019
Publication typeA3 Part of a book or another research book

Publication series

NameLecture Notes in Computer Science
PublisherSpringer
Volume11225
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Abstract

Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput.

In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allows more programming freedom than vector processors.

Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it a suitable target for general purpose computing on GPU APIs which have become popular in the recent years.

Publication forum classification

Field of science, Statistics Finland