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Programmable and scalable architecture for graphics processing units

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Programmable and scalable architecture for graphics processing units. / Sanchez de la lama, C.; Jääskeläinen, P.; Takala, J.

In: Lecture Notes in Computer Science, Vol. 5657, 2009, p. 2-11.

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Sanchez de la lama, C. ; Jääskeläinen, P. ; Takala, J. / Programmable and scalable architecture for graphics processing units. In: Lecture Notes in Computer Science. 2009 ; Vol. 5657. pp. 2-11.

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@article{6281e93521ec4223bb05f45356463806,
title = "Programmable and scalable architecture for graphics processing units",
abstract = "Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput. In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allowing more programming freedom than vector processors. Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it suitable target for general purpose computing on GPU APIs which have become popular in recent years.",
author = "{Sanchez de la lama}, C. and P. J{\"a}{\"a}skel{\"a}inen and J. Takala",
note = "Contribution: organisation=tkt,FACT1=1",
year = "2009",
doi = "10.1007/978-3-642-03138-0_2",
language = "English",
volume = "5657",
pages = "2--11",
journal = "Lecture Notes in Computer Science",
issn = "0302-9743",
publisher = "Springer Verlag",

}

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TY - JOUR

T1 - Programmable and scalable architecture for graphics processing units

AU - Sanchez de la lama, C.

AU - Jääskeläinen, P.

AU - Takala, J.

N1 - Contribution: organisation=tkt,FACT1=1

PY - 2009

Y1 - 2009

N2 - Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput. In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allowing more programming freedom than vector processors. Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it suitable target for general purpose computing on GPU APIs which have become popular in recent years.

AB - Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput. In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allowing more programming freedom than vector processors. Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it suitable target for general purpose computing on GPU APIs which have become popular in recent years.

U2 - 10.1007/978-3-642-03138-0_2

DO - 10.1007/978-3-642-03138-0_2

M3 - Article

VL - 5657

SP - 2

EP - 11

JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

SN - 0302-9743

ER -