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Programmable receiver architectures for multimode mobile terminals

Research output: Book/ReportDoctoral thesisCollection of Articles

Standard

Programmable receiver architectures for multimode mobile terminals. / Harju, L.

Tampere : Tampere University of Technology, 2006. 88 p. (Tampere University of Technology. Publication; Vol. 604).

Research output: Book/ReportDoctoral thesisCollection of Articles

Harvard

Harju, L 2006, Programmable receiver architectures for multimode mobile terminals. Tampere University of Technology. Publication, vol. 604, Tampere University of Technology, Tampere.

APA

Harju, L. (2006). Programmable receiver architectures for multimode mobile terminals. (Tampere University of Technology. Publication; Vol. 604). Tampere: Tampere University of Technology.

Vancouver

Harju L. Programmable receiver architectures for multimode mobile terminals. Tampere: Tampere University of Technology, 2006. 88 p. (Tampere University of Technology. Publication).

Author

Harju, L. / Programmable receiver architectures for multimode mobile terminals. Tampere : Tampere University of Technology, 2006. 88 p. (Tampere University of Technology. Publication).

Bibtex - Download

@book{b21ef93a260942f18e10e94031cedc3b,
title = "Programmable receiver architectures for multimode mobile terminals",
abstract = "This thesis considers the design of a programmable baseband receiver platform for WCDMA and OFDM mobile terminals. The design challenges introduced by the evolution of wireless systems are highlighted and design methodologies deployed in the platform development are introduced. The receiver algorithms of WCDMA and OFDM receivers are summarized and potential processor based architectures for implementing these algorithms are studied. The Espresso platform is composed of a RISC processor core and three coprocessors. The coprocessor provide the functions needed to implement the WCDMA and OFDM receiver algorithms. The key of the coprocessor approach is the exploitation of the computational similarities of the WCDMA and OFDM receiver algorithms. This enables effective reuse of hardware resources between the WCDMA and OFDM modes of the receiver. The RISC processor is used to initiate the coprocessor functions and to implement symbol rate channel estimation and equalization tasks. The interconnection between the host processor and the coprocessors is realized with a dedicated coprocessor bus which reduces the communication overhead typically associated with memory mapped coprocessor. The programming interface of the platform is implemented with a set of coprocessor functions. Typically application-specific processors require low-level programming which affects negatively to the software development efficiency. The programming interface of the proposed platform is implemented with standard C-language which enables productive software development. The platform architecture and the programming interface constitute a template baseband receiver architecture that can be employed in WCDMA and OFDM receivers. The hardware and the software can be fine tuned to the target application without affecting each other as long as the programming interface is kept unchanged. Thus, the platform enables effective reuse of existing hardware and software implementations.",
author = "L. Harju",
note = "Awarding institution:Tampere University of Technology",
year = "2006",
month = "8",
day = "11",
language = "English",
isbn = "952-15-1618-6",
series = "Tampere University of Technology. Publication",
publisher = "Tampere University of Technology",

}

RIS (suitable for import to EndNote) - Download

TY - BOOK

T1 - Programmable receiver architectures for multimode mobile terminals

AU - Harju, L.

N1 - Awarding institution:Tampere University of Technology

PY - 2006/8/11

Y1 - 2006/8/11

N2 - This thesis considers the design of a programmable baseband receiver platform for WCDMA and OFDM mobile terminals. The design challenges introduced by the evolution of wireless systems are highlighted and design methodologies deployed in the platform development are introduced. The receiver algorithms of WCDMA and OFDM receivers are summarized and potential processor based architectures for implementing these algorithms are studied. The Espresso platform is composed of a RISC processor core and three coprocessors. The coprocessor provide the functions needed to implement the WCDMA and OFDM receiver algorithms. The key of the coprocessor approach is the exploitation of the computational similarities of the WCDMA and OFDM receiver algorithms. This enables effective reuse of hardware resources between the WCDMA and OFDM modes of the receiver. The RISC processor is used to initiate the coprocessor functions and to implement symbol rate channel estimation and equalization tasks. The interconnection between the host processor and the coprocessors is realized with a dedicated coprocessor bus which reduces the communication overhead typically associated with memory mapped coprocessor. The programming interface of the platform is implemented with a set of coprocessor functions. Typically application-specific processors require low-level programming which affects negatively to the software development efficiency. The programming interface of the proposed platform is implemented with standard C-language which enables productive software development. The platform architecture and the programming interface constitute a template baseband receiver architecture that can be employed in WCDMA and OFDM receivers. The hardware and the software can be fine tuned to the target application without affecting each other as long as the programming interface is kept unchanged. Thus, the platform enables effective reuse of existing hardware and software implementations.

AB - This thesis considers the design of a programmable baseband receiver platform for WCDMA and OFDM mobile terminals. The design challenges introduced by the evolution of wireless systems are highlighted and design methodologies deployed in the platform development are introduced. The receiver algorithms of WCDMA and OFDM receivers are summarized and potential processor based architectures for implementing these algorithms are studied. The Espresso platform is composed of a RISC processor core and three coprocessors. The coprocessor provide the functions needed to implement the WCDMA and OFDM receiver algorithms. The key of the coprocessor approach is the exploitation of the computational similarities of the WCDMA and OFDM receiver algorithms. This enables effective reuse of hardware resources between the WCDMA and OFDM modes of the receiver. The RISC processor is used to initiate the coprocessor functions and to implement symbol rate channel estimation and equalization tasks. The interconnection between the host processor and the coprocessors is realized with a dedicated coprocessor bus which reduces the communication overhead typically associated with memory mapped coprocessor. The programming interface of the platform is implemented with a set of coprocessor functions. Typically application-specific processors require low-level programming which affects negatively to the software development efficiency. The programming interface of the proposed platform is implemented with standard C-language which enables productive software development. The platform architecture and the programming interface constitute a template baseband receiver architecture that can be employed in WCDMA and OFDM receivers. The hardware and the software can be fine tuned to the target application without affecting each other as long as the programming interface is kept unchanged. Thus, the platform enables effective reuse of existing hardware and software implementations.

M3 - Doctoral thesis

SN - 952-15-1618-6

T3 - Tampere University of Technology. Publication

BT - Programmable receiver architectures for multimode mobile terminals

PB - Tampere University of Technology

CY - Tampere

ER -