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Statistical traffic properties and model inference for shared cache interface in multi-core CPUs

Research output: Contribution to journalArticleScientificpeer-review

Details

Original languageEnglish
Pages (from-to)4829-4839
Number of pages11
JournalIEEE Access
Volume4
DOIs
Publication statusPublished - 25 Aug 2016
Publication typeA1 Journal article-refereed

Abstract

The general-purpose networks-on-chip (GP-NoC) has recently attracted the attention of the research and industry as a way to support the growing demands of computing systems. The design and the development of the communications and networking functions for such a large-scale versatile systems require knowledge of the traffic exchanged between the computing nodes. The object of the study in this paper is the last-level shared cache interface that is likely to be a traffic bottleneck in future GP-NoC architectures. First, using the direct measurements, we report on the stochastic traffic properties at large-scales, provide first two moments and distribution functions. Complementing measurements with fine-grained cycle-accurate CPU simulations, we then analyze the small-scale traffic behavior. We show that even for the simplest applications such as reading or writing of data, the nature of the traffic is stochastic, depends on the number of active cores, and irrespective of the application type, has an explicit batch structure. We further reveal that the batch sizes and inter-batch intervals can be well approximated by geometric distribution and the approximation becomes better when the number of active cores increases. These properties identify a simple arrival model that can be used in the analytical or simulation-based performance evaluation studies of the shared interface technologies in prospective NoCs.

Keywords

  • cache memory, communication system traffic, Microprocessors, modeling

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