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System-level design for partially reconfigurable hardware

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication2007 IEEE International Symposium on Circuits and Systems
Pages2738-2741
Number of pages4
DOIs
Publication statusPublished - 2007
Publication typeA4 Article in a conference publication
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 200730 May 2007

Conference

Conference2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
CountryUnited States
CityNew Orleans, LA
Period27/05/0730/05/07

Abstract

In this paper, we present a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform.