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TCEMC: A Co-Design Flow for Application-Specific Multicores

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Original languageEnglish
Title of host publicationInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece
EditorsLuigi Garro, Andy D. Pimentel
Place of PublicationPiscataway, NJ
ISBN (Print)978-1-4577-0802-2
Publication statusPublished - 2011
Publication typeA4 Article in a conference publication

Publication series

NameInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos


Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology.

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