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TCEMC: A Co-Design Flow for Application-Specific Multicores

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TCEMC: A Co-Design Flow for Application-Specific Multicores. / Jääskeläinen, Pekka; Salminen, Erno; Sanchez de La Lama, Carlos; Takala, Jarmo; Ignacio Martinez, Jose.

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece. ed. / Luigi Garro; Andy D. Pimentel. Piscataway, NJ : IEEE, 2011. p. 85-92 (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos).

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Jääskeläinen, P, Salminen, E, Sanchez de La Lama, C, Takala, J & Ignacio Martinez, J 2011, TCEMC: A Co-Design Flow for Application-Specific Multicores. in L Garro & AD Pimentel (eds), International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos, IEEE, Piscataway, NJ, pp. 85-92. https://doi.org/10.1109/SAMOS.2011.6045448

APA

Jääskeläinen, P., Salminen, E., Sanchez de La Lama, C., Takala, J., & Ignacio Martinez, J. (2011). TCEMC: A Co-Design Flow for Application-Specific Multicores. In L. Garro, & A. D. Pimentel (Eds.), International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece (pp. 85-92). (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos). Piscataway, NJ: IEEE. https://doi.org/10.1109/SAMOS.2011.6045448

Vancouver

Jääskeläinen P, Salminen E, Sanchez de La Lama C, Takala J, Ignacio Martinez J. TCEMC: A Co-Design Flow for Application-Specific Multicores. In Garro L, Pimentel AD, editors, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece. Piscataway, NJ: IEEE. 2011. p. 85-92. (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos). https://doi.org/10.1109/SAMOS.2011.6045448

Author

Jääskeläinen, Pekka ; Salminen, Erno ; Sanchez de La Lama, Carlos ; Takala, Jarmo ; Ignacio Martinez, Jose. / TCEMC: A Co-Design Flow for Application-Specific Multicores. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece. editor / Luigi Garro ; Andy D. Pimentel. Piscataway, NJ : IEEE, 2011. pp. 85-92 (International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos).

Bibtex - Download

@inproceedings{032dcfd3464c4c82adaa9344a9c345fc,
title = "TCEMC: A Co-Design Flow for Application-Specific Multicores",
abstract = "Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology.",
author = "Pekka J{\"a}{\"a}skel{\"a}inen and Erno Salminen and {Sanchez de La Lama}, Carlos and Jarmo Takala and {Ignacio Martinez}, Jose",
note = "ei ut-numeroa 15.3.2014<br/>Contribution: organisation=tkt,FACT1=1",
year = "2011",
doi = "10.1109/SAMOS.2011.6045448",
language = "English",
isbn = "978-1-4577-0802-2",
series = "International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos",
publisher = "IEEE",
pages = "85--92",
editor = "Luigi Garro and Pimentel, {Andy D.}",
booktitle = "International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece",

}

RIS (suitable for import to EndNote) - Download

TY - GEN

T1 - TCEMC: A Co-Design Flow for Application-Specific Multicores

AU - Jääskeläinen, Pekka

AU - Salminen, Erno

AU - Sanchez de La Lama, Carlos

AU - Takala, Jarmo

AU - Ignacio Martinez, Jose

N1 - ei ut-numeroa 15.3.2014<br/>Contribution: organisation=tkt,FACT1=1

PY - 2011

Y1 - 2011

N2 - Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology.

AB - Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology.

U2 - 10.1109/SAMOS.2011.6045448

DO - 10.1109/SAMOS.2011.6045448

M3 - Conference contribution

SN - 978-1-4577-0802-2

T3 - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation IC-Samos

SP - 85

EP - 92

BT - International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-Samos, 2011, July 18-21, 2011, Samos, Greece

A2 - Garro, Luigi

A2 - Pimentel, Andy D.

PB - IEEE

CY - Piscataway, NJ

ER -