The Evolution of Software-Defined Radio: An Introduction
Research output: Chapter in Book/Report/Conference proceeding › Chapter › Scientific › peer-review
|Title of host publication||Computing Platforms for Software-Defined Radio|
|Editors||Waqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia|
|Publication status||Published - 2017|
|Publication type||A3 Part of a book or another research book|
The Software-Defined Radio (SDR) concept was originally developed by the combined efforts of various research groups in the private and government organizations of the United States (US) in 1970s–1980s. The important ones to mention are the US Department of Defense Laboratory and a team at the Garland, Texas Division of E-Systems Inc. In 1991, Joe Mitola independently reinvented the term ‘Software Radio’ (SR) in cooperation with E-Systems as a plan to build a true software-based GSM transceiver (Mitola, Telesystems Conference, 1992). The SR platform essentially processes almost all the transceiver algorithms as software for a processor. This includes nearly all layers of transmission. However, an optimal implementation of physical layer is always challenging due to an enormous amount of mathematical computation. Over the period of time, many developmental changes occurred and an interesting feature of cognition was added to existing SDR platforms, thereby inventing the term ‘Cognitive Radio’. The main idea was to reduce over-sampling by the analog to digital converter, reduce on-chip processing and to target only the spectrum of interest. This book also touches the CR feature in the large SDR field in some of its selected chapters. Since, the very first few articles of J. Mitola, there has a been a tremendous amount of research work conducted in industry and academia. The evolution in SDRs is continuous with time and provides a number of excellent opportunities to researcher for exploration and to come up with their findings. The present day SDR implementations are such that the designers are focused mostly on the design of hardware and software, their interfacing and optimizations for varying architectural choices. It includes multiple cases of application-specific general-purpose acceleration platforms that are scalable, homogeneous and heterogeneous in nature while providing multiple programmable cores on a single chip computing system.