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Variable Length Instruction Compression on Transport Triggered Architectures

Research output: Scientific - peer-reviewConference contribution

Standard

Variable Length Instruction Compression on Transport Triggered Architectures. / Helkala, Janne; Viitanen, Timo; Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo; Zetterman, Tommi; Berg, Heikki.

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014. Institute of Electrical and Electronics Engineers IEEE, 2014. p. 149-155.

Research output: Scientific - peer-reviewConference contribution

Harvard

Helkala, J, Viitanen, T, Kultala, H, Jääskeläinen, P, Takala, J, Zetterman, T & Berg, H 2014, Variable Length Instruction Compression on Transport Triggered Architectures. in 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014. Institute of Electrical and Electronics Engineers IEEE, pp. 149-155, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, 1 January.

APA

Helkala, J., Viitanen, T., Kultala, H., Jääskeläinen, P., Takala, J., Zetterman, T., & Berg, H. (2014). Variable Length Instruction Compression on Transport Triggered Architectures. In 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014 (pp. 149-155). Institute of Electrical and Electronics Engineers IEEE.

Vancouver

Helkala J, Viitanen T, Kultala H, Jääskeläinen P, Takala J, Zetterman T et al. Variable Length Instruction Compression on Transport Triggered Architectures. In 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014. Institute of Electrical and Electronics Engineers IEEE. 2014. p. 149-155.

Author

Helkala, Janne; Viitanen, Timo; Kultala, Heikki; Jääskeläinen, Pekka; Takala, Jarmo; Zetterman, Tommi; Berg, Heikki / Variable Length Instruction Compression on Transport Triggered Architectures.

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014. Institute of Electrical and Electronics Engineers IEEE, 2014. p. 149-155.

Research output: Scientific - peer-reviewConference contribution

Bibtex - Download

@inbook{53ed819737944598a144df41bc83a991,
title = "Variable Length Instruction Compression on Transport Triggered Architectures",
abstract = "The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The power saved using compression is easily lost on inefficient processor design. We propose an implementation for instruction template -based compression and two instruction fetch alternatives for variable length instruction encoding on Transport Triggered Architecture, a static multiple-issue exposed data path architecture. The compression approach reaches an average program size reduction of 44% at best. We show that the variable length fetch designs are sufficiently low-power oriented for the system to benefit from the code compression, which reduces the program memory size.",
author = "Janne Helkala and Timo Viitanen and Heikki Kultala and Pekka Jääskeläinen and Jarmo Takala and Tommi Zetterman and Heikki Berg",
note = "Contribution: organisation=tie,FACT1=1<br/>Portfolio EDEND: 2014-08-23<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE",
year = "2014",
isbn = "978-1-4799-3770-7",
pages = "149--155",
booktitle = "2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014",
publisher = "Institute of Electrical and Electronics Engineers IEEE",

}

RIS (suitable for import to EndNote) - Download

TY - CHAP

T1 - Variable Length Instruction Compression on Transport Triggered Architectures

AU - Helkala,Janne

AU - Viitanen,Timo

AU - Kultala,Heikki

AU - Jääskeläinen,Pekka

AU - Takala,Jarmo

AU - Zetterman,Tommi

AU - Berg,Heikki

N1 - Contribution: organisation=tie,FACT1=1<br/>Portfolio EDEND: 2014-08-23<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE

PY - 2014

Y1 - 2014

N2 - The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The power saved using compression is easily lost on inefficient processor design. We propose an implementation for instruction template -based compression and two instruction fetch alternatives for variable length instruction encoding on Transport Triggered Architecture, a static multiple-issue exposed data path architecture. The compression approach reaches an average program size reduction of 44% at best. We show that the variable length fetch designs are sufficiently low-power oriented for the system to benefit from the code compression, which reduces the program memory size.

AB - The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The power saved using compression is easily lost on inefficient processor design. We propose an implementation for instruction template -based compression and two instruction fetch alternatives for variable length instruction encoding on Transport Triggered Architecture, a static multiple-issue exposed data path architecture. The compression approach reaches an average program size reduction of 44% at best. We show that the variable length fetch designs are sufficiently low-power oriented for the system to benefit from the code compression, which reduces the program memory size.

M3 - Conference contribution

SN - 978-1-4799-3770-7

SP - 149

EP - 155

BT - 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014

PB - Institute of Electrical and Electronics Engineers IEEE

ER -