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Variable Length Instruction Compression on Transport Triggered Architectures

Research output: Contribution to journalArticleScientificpeer-review


Original languageEnglish
Pages (from-to)1283-1303
Number of pages21
JournalInternational Journal of Parallel Programming
Issue number6
Early online date6 Apr 2018
Publication statusPublished - Dec 2018
Publication typeA1 Journal article-refereed


The memories used for embedded microprocessor devices consume a large portion of the system’s power. The power dissipation of the instruction memory can be reduced by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The memory-side power savings using compression are easily lost on inefficient fetch unit design. We propose an implementation for instruction template-based compression and two instruction fetch alternatives for variable length instruction encoding on transport triggered architecture, a static multiple-issue exposed data path architecture. With applications from the CHStone benchmark suite, the compression approach reaches an average compression ratio of 44% at best. We show that the variable length fetch designs reduce the number of memory accesses and often allow the use of a smaller memory component. The proposed compression scheme reduced the energy consumption of synthesized benchmark processors by 15% and area by 33% on average.


  • Transport triggered architecture, Instruction compression, Instruction fetch, Embedded systems

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Field of science, Statistics Finland

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