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Visualization of memory map information in embedded system design

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationProceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
PublisherIEEE
Pages163-166
Number of pages4
ISBN (Electronic)9781538673768
DOIs
Publication statusPublished - 12 Oct 2018
Publication typeA4 Article in a conference publication
EventEuromicro Conference on Digital System Design - Prague, Czech Republic
Duration: 29 Aug 201831 Aug 2018

Conference

ConferenceEuromicro Conference on Digital System Design
CountryCzech Republic
CityPrague
Period29/08/1831/08/18

Abstract

Data compression is a common requirement for displaying large amounts of information. The goal is to reduce visual clutter. The approach given in this paper uses an analysis of a data set to construct a visual representation. The visualization is compressed using the address ranges of the memory structure. This method produces a compressed version of the initial visualization, retaining the same information as the original. The presented method has been implemented as a Memory Designer tool for ASIC, FPGA and embedded systems using IP-XACT. The Memory Designer is a user-friendly tool for model based embedded system design, providing access and adjustment of the memory layout from a single view, complementing the 'programmer's view' to the system.

ASJC Scopus subject areas

Keywords

  • Compression, Data visualization, Display space, Filtering, Memory structure

Publication forum classification

Field of science, Statistics Finland