Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
|Title of host publication||2016 IEEE International Workshop on Signal Processing Systems (SiPS)|
|Number of pages||6|
|Publication status||Published - 12 Dec 2016|
|Publication type||A4 Article in a conference publication|
|Event||IEEE International Workshop on Signal Processing Systems - |
Duration: 1 Jan 1900 → …
|Conference||IEEE International Workshop on Signal Processing Systems|
|Period||1/01/00 → …|
This paper proposes a method that exploits such contemporary low power SRAM memories that are energy optimized for storing a certain logic value to improve the energy-efficiency of instruction fetching, a major energy overhead in programmable designs. The method utilizes a low overhead xor-masking approach combined with statistical program analysis to produce optimal masks to reduce the occurrence of the more energy consuming bit values in the fetched instructions.
In comparison to the "bus invert" technique typically used with similar SRAMs, the proposed method incurs minimal area overhead while still reducing the total energy consumption of an example LatticeMico32 core up to 5%. The improvement to instruction memory energy consumption alone is up to 13% with a set of benchmarks.