Tampere University of Technology

TUTCRIS Research Portal

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies

Research output: Scientific - peer-reviewConference contribution

Standard

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies. / Multanen, Joonas; Viitanen, Timo; Jääskeläinen, Pekka; Takala, Jarmo.

2016 IEEE International Workshop on Signal Processing Systems (SiPS). IEEE, 2016.

Research output: Scientific - peer-reviewConference contribution

Harvard

Multanen, J, Viitanen, T, Jääskeläinen, P & Takala, J 2016, Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies. in 2016 IEEE International Workshop on Signal Processing Systems (SiPS). IEEE, IEEE International Workshop on Signal Processing Systems, 1 January. DOI: 10.1109/SiPS.2016.19

APA

Vancouver

Author

Multanen, Joonas; Viitanen, Timo; Jääskeläinen, Pekka; Takala, Jarmo / Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies.

2016 IEEE International Workshop on Signal Processing Systems (SiPS). IEEE, 2016.

Research output: Scientific - peer-reviewConference contribution

Bibtex - Download

@inbook{19ae3d1c4d0b44e6a6282a0ab510fa53,
title = "Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies",
author = "Joonas Multanen and Timo Viitanen and Pekka Jääskeläinen and Jarmo Takala",
year = "2016",
month = "12",
doi = "10.1109/SiPS.2016.19",
publisher = "IEEE",
booktitle = "2016 IEEE International Workshop on Signal Processing Systems (SiPS)",

}

RIS (suitable for import to EndNote) - Download

TY - CHAP

T1 - Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies

AU - Multanen,Joonas

AU - Viitanen,Timo

AU - Jääskeläinen,Pekka

AU - Takala,Jarmo

PY - 2016/12/12

Y1 - 2016/12/12

N2 - Pervasive computing calls for ultra-low-power devices to extend the battery life enough to enable usability in everyday life. Especially in devices involving programmable processors, the energy consumption of integrated memories often plays a critical role. Consequently, contemporary memory technologies focus more on the energy-efficiency aspects with new custom CMOS SRAM cells with tailored energy consumption profiles constantly being proposed.<br/><br/>This paper proposes a method that exploits such contemporary low power SRAM memories that are energy optimized for storing a certain logic value to improve the energy-efficiency of instruction fetching, a major energy overhead in programmable designs. The method utilizes a low overhead xor-masking approach combined with statistical program analysis to produce optimal masks to reduce the occurrence of the more energy consuming bit values in the fetched instructions.<br/><br/>In comparison to the "bus invert" technique typically used with similar SRAMs, the proposed method incurs minimal area overhead while still reducing the total energy consumption of an example LatticeMico32 core up to 5%. The improvement to instruction memory energy consumption alone is up to 13% with a set of benchmarks.

AB - Pervasive computing calls for ultra-low-power devices to extend the battery life enough to enable usability in everyday life. Especially in devices involving programmable processors, the energy consumption of integrated memories often plays a critical role. Consequently, contemporary memory technologies focus more on the energy-efficiency aspects with new custom CMOS SRAM cells with tailored energy consumption profiles constantly being proposed.<br/><br/>This paper proposes a method that exploits such contemporary low power SRAM memories that are energy optimized for storing a certain logic value to improve the energy-efficiency of instruction fetching, a major energy overhead in programmable designs. The method utilizes a low overhead xor-masking approach combined with statistical program analysis to produce optimal masks to reduce the occurrence of the more energy consuming bit values in the fetched instructions.<br/><br/>In comparison to the "bus invert" technique typically used with similar SRAMs, the proposed method incurs minimal area overhead while still reducing the total energy consumption of an example LatticeMico32 core up to 5%. The improvement to instruction memory energy consumption alone is up to 13% with a set of benchmarks.

U2 - 10.1109/SiPS.2016.19

DO - 10.1109/SiPS.2016.19

M3 - Conference contribution

BT - 2016 IEEE International Workshop on Signal Processing Systems (SiPS)

PB - IEEE

ER -