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90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation

Tutkimustuotosvertaisarvioitu

Standard

90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation. / Ramesh, Anisha; Park, Si Young; Berger, Paul R.

julkaisussa: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, Vuosikerta 58, Nro 10, 2011, s. 2432-2445.

Tutkimustuotosvertaisarvioitu

Harvard

Ramesh, A, Park, SY & Berger, PR 2011, '90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation', IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, Vuosikerta. 58, Nro 10, Sivut 2432-2445. https://doi.org/10.1109/TCSI.2011.2123630

APA

Ramesh, A., Park, S. Y., & Berger, P. R. (2011). 90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation. IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, 58(10), 2432-2445. https://doi.org/10.1109/TCSI.2011.2123630

Vancouver

Ramesh A, Park SY, Berger PR. 90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation. IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2011;58(10):2432-2445. https://doi.org/10.1109/TCSI.2011.2123630

Author

Ramesh, Anisha ; Park, Si Young ; Berger, Paul R. / 90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation. Julkaisussa: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 2011 ; Vuosikerta 58, Nro 10. Sivut 2432-2445.

Bibtex - Lataa

@article{3c9920d7240c44cf86891c5a5b2169de,
title = "90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation",
abstract = "Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic 1 and 0 V as a logic 0. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6× 10-5mW per cell and dynamic power dissipation of &1.8× 10-7mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.",
keywords = "Embedded memory, low power memory, negative differential resistance (NDR), resonant interband tunnel diodes, tunnel diodes, tunnel static random access memory (SRAM)",
author = "Anisha Ramesh and Park, {Si Young} and Berger, {Paul R.}",
year = "2011",
doi = "10.1109/TCSI.2011.2123630",
language = "English",
volume = "58",
pages = "2432--2445",
journal = "IEEE Transactions on Circuits and Systems. Part 1: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers",
number = "10",

}

RIS (suitable for import to EndNote) - Lataa

TY - JOUR

T1 - 90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation

AU - Ramesh, Anisha

AU - Park, Si Young

AU - Berger, Paul R.

PY - 2011

Y1 - 2011

N2 - Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic 1 and 0 V as a logic 0. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6× 10-5mW per cell and dynamic power dissipation of &1.8× 10-7mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.

AB - Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic 1 and 0 V as a logic 0. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6× 10-5mW per cell and dynamic power dissipation of &1.8× 10-7mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.

KW - Embedded memory

KW - low power memory

KW - negative differential resistance (NDR)

KW - resonant interband tunnel diodes

KW - tunnel diodes

KW - tunnel static random access memory (SRAM)

U2 - 10.1109/TCSI.2011.2123630

DO - 10.1109/TCSI.2011.2123630

M3 - Article

VL - 58

SP - 2432

EP - 2445

JO - IEEE Transactions on Circuits and Systems. Part 1: Regular Papers

JF - IEEE Transactions on Circuits and Systems. Part 1: Regular Papers

SN - 1549-8328

IS - 10

ER -