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A custom processor for protocol-independent packet parsing

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A custom processor for protocol-independent packet parsing. / Zolfaghari, Hesam; Rossi, Davide; Nurmi, Jari.

julkaisussa: Microprocessors and Microsystems, Vuosikerta 72, 01.02.2020.

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Zolfaghari, Hesam ; Rossi, Davide ; Nurmi, Jari. / A custom processor for protocol-independent packet parsing. Julkaisussa: Microprocessors and Microsystems. 2020 ; Vuosikerta 72.

Bibtex - Lataa

@article{da7fe45449064d1da3df37cc0f264b09,
title = "A custom processor for protocol-independent packet parsing",
abstract = "Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5.",
keywords = "Advanced program control, Packet parsing, Programmable data plane, Software defined networking",
author = "Hesam Zolfaghari and Davide Rossi and Jari Nurmi",
year = "2020",
month = "2",
day = "1",
doi = "10.1016/j.micpro.2019.102910",
language = "English",
volume = "72",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",

}

RIS (suitable for import to EndNote) - Lataa

TY - JOUR

T1 - A custom processor for protocol-independent packet parsing

AU - Zolfaghari, Hesam

AU - Rossi, Davide

AU - Nurmi, Jari

PY - 2020/2/1

Y1 - 2020/2/1

N2 - Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5.

AB - Networking devices such as switches and routers have traditionally had fixed functionality. They have the logic for the union of network protocols matching the application and market segment for which they have been designed. Possibility of adding new functionality is limited. One of the aims of Software Defined Networking is to make packet processing devices programmable. This provides for innovation and rapid deployment of novel networking protocols. The first step in processing of packets is packet parsing. In this paper, we present a custom processor for packet parsing. The parser is protocol-independent and can be programmed to parse any sequence of headers. It does so without the use of a Ternary Content Addressable Memory. As a result, the area and power consumption are noticeably smaller than in the state of the art. Moreover, its output is the same as that of the parser used in the Reconfigurable Match Tables (RMT). With an area no more than that of parsers in the RMT architecture, it sustains aggregate throughput of 3.4 Tbps in the worst case which is an improvement by a factor of 5.

KW - Advanced program control

KW - Packet parsing

KW - Programmable data plane

KW - Software defined networking

U2 - 10.1016/j.micpro.2019.102910

DO - 10.1016/j.micpro.2019.102910

M3 - Article

VL - 72

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

ER -