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A design framework for mapping vectorized synchronous dataflow graphs onto CPU-GPU platforms

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Yksityiskohdat

AlkuperäiskieliEnglanti
OtsikkoProceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2016
KustantajaACM
Sivut20-29
Sivumäärä10
ISBN (painettu)9781450343206
DOI - pysyväislinkit
TilaJulkaistu - 23 toukokuuta 2016
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaINTERNATIONAL WORKSHOP ON SOFTWARE AND COMPILERS FOR EMBEDDED SYSTEMS -
Kesto: 1 tammikuuta 1900 → …

Conference

ConferenceINTERNATIONAL WORKSHOP ON SOFTWARE AND COMPILERS FOR EMBEDDED SYSTEMS
Ajanjakso1/01/00 → …

Tiivistelmä

Heterogeneous computing platforms with multicore central processing units (CPUs) and graphics processing units (GPUs) are of increasing interest to designers of embedded signal processing systems since they offer the potential for significant performance boost while maintaining the flexibility of software-based design flows. Developing optimized implementations for CPU-GPU platforms is challenging due to complex, inter-related design issues, including task scheduling, interprocessor communication, memory management, and modeling and exploitation of different forms of parallelism. In this paper, we present an automated, dataflow based, design framework called DIF-GPU for application mapping and software synthesis on heterogeneous CPU-GPU platforms. DIF-GPU is based on novel extensions to the dataflow interchange format (DIF) package, which is a software environment for developing and experimenting with dataflow-based design methods and synthesis techniques for embedded signal processing systems. DIF-GPU exploits multiple forms of parallelism by deeply incorporating efficient vectorization and scheduling techniques for synchronous dataflow specifications, and incorporating techniques for streamlining interprocessor communication. DIF-GPU also provides software synthesis capabilities to help accelerate the process of moving from high-level application models to optimized implementations.

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