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A High-Speed DSP Engine for First-Order Hold Digital Phase Modulation in 28-nm CMOS

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Yksityiskohdat

AlkuperäiskieliEnglanti
Sivut1959-1963
JulkaisuIEEE Transactions on Circuits and Systems II: Express Briefs
Vuosikerta65
Numero12
DOI - pysyväislinkit
TilaJulkaistu - joulukuuta 2018
OKM-julkaisutyyppiA1 Alkuperäisartikkeli

Tiivistelmä

Conventional delay-based digital phase modulators use a zero-order hold (ZOH) phase control word to modulate the square-wave RF carrier. Recently, new architectures capable of performing first-order hold (FOH) digital phase modulation have been proposed, thus improving the wideband performance to a level suitable for 5G base stations. While currently available literature focuses on the generic operation principle, this brief details the first on-chip implementation of the DSP engine required for actual FOH computations. The circuit is based on a simple iterative algorithm, which can be pipelined for high-speed operation. The DSP engine has been integrated as part of a prototype 5G base-station outphasing transmitter, fabricated in 28-nm CMOS. When processing a 100-MHz orthogonal frequency-division multiplexing signal, the DSP achieves an adjacent-channel leakage ratio of –53 dBc, which is 12 dB better than with conventional ZOH phase modulation. Furthermore, the system enables flexible upconversion to any frequency between 0.35 and 2.1 GHz from a fixed 1.5-GHz reference clock. The power consumption of a single engine is lower than 18 mW.

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