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Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

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Standard

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. / Yviquel, Hervé; Boutellier, Jani; Raulet, Mickaël; Casseau, Emmanuel.

julkaisussa: Signal Processing: Image Communication, Vuosikerta 28, Nro 10, 11.2013, s. 1295-1302.

Tutkimustuotosvertaisarvioitu

Harvard

Yviquel, H, Boutellier, J, Raulet, M & Casseau, E 2013, 'Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs', Signal Processing: Image Communication, Vuosikerta. 28, Nro 10, Sivut 1295-1302. https://doi.org/10.1016/j.image.2013.08.013

APA

Yviquel, H., Boutellier, J., Raulet, M., & Casseau, E. (2013). Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. Signal Processing: Image Communication, 28(10), 1295-1302. https://doi.org/10.1016/j.image.2013.08.013

Vancouver

Yviquel H, Boutellier J, Raulet M, Casseau E. Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. Signal Processing: Image Communication. 2013 marras;28(10):1295-1302. https://doi.org/10.1016/j.image.2013.08.013

Author

Yviquel, Hervé ; Boutellier, Jani ; Raulet, Mickaël ; Casseau, Emmanuel. / Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs. Julkaisussa: Signal Processing: Image Communication. 2013 ; Vuosikerta 28, Nro 10. Sivut 1295-1302.

Bibtex - Lataa

@article{a62e128528a34d3899aef790ec8c81bd,
title = "Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs",
abstract = "Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems. This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism. The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50 MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.",
keywords = "Co-design, Dataflow programming, Multi-Processor System-on-Chip (MPSoC), Reconfigurable Video Coding (RVC), Transport-Trigger Architecture (TTA)",
author = "Herv{\'e} Yviquel and Jani Boutellier and Micka{\"e}l Raulet and Emmanuel Casseau",
year = "2013",
month = "11",
doi = "10.1016/j.image.2013.08.013",
language = "English",
volume = "28",
pages = "1295--1302",
journal = "Signal Processing: Image Communication",
issn = "0923-5965",
publisher = "Elsevier",
number = "10",

}

RIS (suitable for import to EndNote) - Lataa

TY - JOUR

T1 - Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

AU - Yviquel, Hervé

AU - Boutellier, Jani

AU - Raulet, Mickaël

AU - Casseau, Emmanuel

PY - 2013/11

Y1 - 2013/11

N2 - Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems. This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism. The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50 MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.

AB - Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems. This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism. The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50 MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism.

KW - Co-design

KW - Dataflow programming

KW - Multi-Processor System-on-Chip (MPSoC)

KW - Reconfigurable Video Coding (RVC)

KW - Transport-Trigger Architecture (TTA)

UR - http://www.scopus.com/inward/record.url?scp=84888203042&partnerID=8YFLogxK

U2 - 10.1016/j.image.2013.08.013

DO - 10.1016/j.image.2013.08.013

M3 - Article

VL - 28

SP - 1295

EP - 1302

JO - Signal Processing: Image Communication

JF - Signal Processing: Image Communication

SN - 0923-5965

IS - 10

ER -