Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs
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Yksityiskohdat
| Alkuperäiskieli | Englanti |
|---|---|
| Otsikko | 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings |
| Sivut | 25-30 |
| Sivumäärä | 6 |
| DOI - pysyväislinkit | |
| Tila | Julkaistu - 2011 |
| OKM-julkaisutyyppi | A4 Artikkeli konferenssijulkaisussa |
| Tapahtuma | 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 - Beirut, Libanon Kesto: 4 lokakuuta 2011 → 7 lokakuuta 2011 |
Conference
| Conference | 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 |
|---|---|
| Maa | Libanon |
| Kaupunki | Beirut |
| Ajanjakso | 4/10/11 → 7/10/11 |
Tiivistelmä
The RVC-CAL dataflow language has recently become standardized through its use as the official language of Recon-figurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transformation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruction processors and HDL synthesis. This paper introduces new tools that enable automatic creation of heterogeneous multiprocessor networks out of RVC-CAL dataflow programs. Each processor in the network performs the functionality of one RVC-CAL actor. The processors are of the Transport Triggered Architecture (TTA) type, for which a complete co-design toolset exists. The existing tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the tool chain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. This particular decoder is automatically realized into 21 tiny, heterogeneous processors.