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Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs

Tutkimustuotosvertaisarvioitu

Standard

Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs. / Boutellier, J.; Silvén, O.; Raulet, M.

2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. 2011. s. 25-30 6088944.

Tutkimustuotosvertaisarvioitu

Harvard

Boutellier, J, Silvén, O & Raulet, M 2011, Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs. julkaisussa 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings., 6088944, Sivut 25-30, Beirut, Libanon, 4/10/11. https://doi.org/10.1109/SiPS.2011.6088944

APA

Boutellier, J., Silvén, O., & Raulet, M. (2011). Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs. teoksessa 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings (Sivut 25-30). [6088944] https://doi.org/10.1109/SiPS.2011.6088944

Vancouver

Boutellier J, Silvén O, Raulet M. Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs. julkaisussa 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. 2011. s. 25-30. 6088944 https://doi.org/10.1109/SiPS.2011.6088944

Author

Boutellier, J. ; Silvén, O. ; Raulet, M. / Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs. 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. 2011. Sivut 25-30

Bibtex - Lataa

@inproceedings{6e2a18e7977b4b3f892cf72a45f13d65,
title = "Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs",
abstract = "The RVC-CAL dataflow language has recently become standardized through its use as the official language of Recon-figurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transformation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruction processors and HDL synthesis. This paper introduces new tools that enable automatic creation of heterogeneous multiprocessor networks out of RVC-CAL dataflow programs. Each processor in the network performs the functionality of one RVC-CAL actor. The processors are of the Transport Triggered Architecture (TTA) type, for which a complete co-design toolset exists. The existing tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the tool chain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. This particular decoder is automatically realized into 21 tiny, heterogeneous processors.",
keywords = "data flow computing, design automation, multiprocessor interconnection",
author = "J. Boutellier and O. Silv{\'e}n and M. Raulet",
year = "2011",
doi = "10.1109/SiPS.2011.6088944",
language = "English",
isbn = "9781457719219",
pages = "25--30",
booktitle = "2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings",

}

RIS (suitable for import to EndNote) - Lataa

TY - GEN

T1 - Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs

AU - Boutellier, J.

AU - Silvén, O.

AU - Raulet, M.

PY - 2011

Y1 - 2011

N2 - The RVC-CAL dataflow language has recently become standardized through its use as the official language of Recon-figurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transformation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruction processors and HDL synthesis. This paper introduces new tools that enable automatic creation of heterogeneous multiprocessor networks out of RVC-CAL dataflow programs. Each processor in the network performs the functionality of one RVC-CAL actor. The processors are of the Transport Triggered Architecture (TTA) type, for which a complete co-design toolset exists. The existing tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the tool chain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. This particular decoder is automatically realized into 21 tiny, heterogeneous processors.

AB - The RVC-CAL dataflow language has recently become standardized through its use as the official language of Recon-figurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transformation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruction processors and HDL synthesis. This paper introduces new tools that enable automatic creation of heterogeneous multiprocessor networks out of RVC-CAL dataflow programs. Each processor in the network performs the functionality of one RVC-CAL actor. The processors are of the Transport Triggered Architecture (TTA) type, for which a complete co-design toolset exists. The existing tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the tool chain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. This particular decoder is automatically realized into 21 tiny, heterogeneous processors.

KW - data flow computing

KW - design automation

KW - multiprocessor interconnection

UR - http://www.scopus.com/inward/record.url?scp=84055198564&partnerID=8YFLogxK

U2 - 10.1109/SiPS.2011.6088944

DO - 10.1109/SiPS.2011.6088944

M3 - Conference contribution

SN - 9781457719219

SP - 25

EP - 30

BT - 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings

ER -