TUTCRIS - Tampereen teknillinen yliopisto

TUTCRIS

Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits

Tutkimustuotos: Konferenssiesitys, posteri tai abstrakti

Yksityiskohdat

AlkuperäiskieliEnglanti
Sivumäärä6
DOI - pysyväislinkit
TilaJulkaistu - 4 huhtikuuta 2019
Julkaistu ulkoisestiKyllä
OKM-julkaisutyyppiEi OKM-tyyppiä
Tapahtuma2018 Conference on Design of Circuits and Integrated Systems - Lyon, Ranska
Kesto: 14 marraskuuta 201816 marraskuuta 2018
Konferenssinumero: XXIII

Conference

Conference2018 Conference on Design of Circuits and Integrated Systems
LyhennettäDCIS
MaaRanska
KaupunkiLyon
Ajanjakso14/11/1816/11/18

Tiivistelmä

The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.