TUTCRIS - Tampereen teknillinen yliopisto

TUTCRIS

Chip-by-chip configurable interconnection using digital printing techniques

Tutkimustuotosvertaisarvioitu

Standard

Chip-by-chip configurable interconnection using digital printing techniques. / Mashayekhi, Mohammad; Winchester, Lee; Laurila, Mika-Matti; Mäntysalo, Matti; Ogier, Simon; Terés, Lluís; Carrabina, Jordi.

julkaisussa: Journal of Micromechanics and Microengineering, Vuosikerta 27, Nro 4, 045009, 06.03.2017.

Tutkimustuotosvertaisarvioitu

Harvard

Mashayekhi, M, Winchester, L, Laurila, M-M, Mäntysalo, M, Ogier, S, Terés, L & Carrabina, J 2017, 'Chip-by-chip configurable interconnection using digital printing techniques', Journal of Micromechanics and Microengineering, Vuosikerta. 27, Nro 4, 045009. https://doi.org/10.1088/1361-6439/aa5ef3

APA

Mashayekhi, M., Winchester, L., Laurila, M-M., Mäntysalo, M., Ogier, S., Terés, L., & Carrabina, J. (2017). Chip-by-chip configurable interconnection using digital printing techniques. Journal of Micromechanics and Microengineering, 27(4), [045009]. https://doi.org/10.1088/1361-6439/aa5ef3

Vancouver

Mashayekhi M, Winchester L, Laurila M-M, Mäntysalo M, Ogier S, Terés L et al. Chip-by-chip configurable interconnection using digital printing techniques. Journal of Micromechanics and Microengineering. 2017 maalis 6;27(4). 045009. https://doi.org/10.1088/1361-6439/aa5ef3

Author

Mashayekhi, Mohammad ; Winchester, Lee ; Laurila, Mika-Matti ; Mäntysalo, Matti ; Ogier, Simon ; Terés, Lluís ; Carrabina, Jordi. / Chip-by-chip configurable interconnection using digital printing techniques. Julkaisussa: Journal of Micromechanics and Microengineering. 2017 ; Vuosikerta 27, Nro 4.

Bibtex - Lataa

@article{8fabc766028b4204a85fe203a7982df5,
title = "Chip-by-chip configurable interconnection using digital printing techniques",
abstract = "Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results.",
keywords = "digital circuits, digital printing, drop-on-demand, inkjet, inkjet configurable gate array, interconnection, printed electronics",
author = "Mohammad Mashayekhi and Lee Winchester and Mika-Matti Laurila and Matti M{\"a}ntysalo and Simon Ogier and Llu{\'i}s Ter{\'e}s and Jordi Carrabina",
year = "2017",
month = "3",
day = "6",
doi = "10.1088/1361-6439/aa5ef3",
language = "English",
volume = "27",
journal = "Journal of Micromechanics and Microengineering",
issn = "0960-1317",
publisher = "IOP Publishing",
number = "4",

}

RIS (suitable for import to EndNote) - Lataa

TY - JOUR

T1 - Chip-by-chip configurable interconnection using digital printing techniques

AU - Mashayekhi, Mohammad

AU - Winchester, Lee

AU - Laurila, Mika-Matti

AU - Mäntysalo, Matti

AU - Ogier, Simon

AU - Terés, Lluís

AU - Carrabina, Jordi

PY - 2017/3/6

Y1 - 2017/3/6

N2 - Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results.

AB - Printed electronics technologies add new fabrication concepts to the classical set of microelectronic processes. Among these, the use of digital printing techniques such as inkjet permits the deposition of materials on top of preexisting substrates without any mask. This allows individual personalization of electronic circuits. Different proposals have been made to make use of such a property: (1) wiring new metallic layers on top of circuits to build programmable logic array-like circuits, (2) programming OTP ROM like memories, and (3) building inkjet-configurable gate arrays. The capability of building an individual circuit with technological steps simpler than photolithographic ones opens a concept similar to the successful field programmable gate array. Although nowadays the process resolution is still low, it can quickly evolve to higher wiring densities and therefore permit a greater level of transistor integration. In this paper, we propose a new structure to realize the connections only by deposition of conductive dots oriented to optimize the area needed to implement the drop-on-demand (DoD) wiring at circuit level. One important feature of this structure is that it minimizes the amount of printed material required for the connection thereby reducing failures often seen with DoD printing techniques for conductive lines. These structures have been validated by two different DoD technologies: inkjet and superfine jet, and have been compared to mask-based photolithography technology with promising results.

KW - digital circuits

KW - digital printing

KW - drop-on-demand

KW - inkjet

KW - inkjet configurable gate array

KW - interconnection

KW - printed electronics

U2 - 10.1088/1361-6439/aa5ef3

DO - 10.1088/1361-6439/aa5ef3

M3 - Article

VL - 27

JO - Journal of Micromechanics and Microengineering

JF - Journal of Micromechanics and Microengineering

SN - 0960-1317

IS - 4

M1 - 045009

ER -