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Customized High Performance Low Power Processor for Binaural Speaker Localization

Tutkimustuotosvertaisarvioitu

Yksityiskohdat

AlkuperäiskieliEnglanti
Otsikko2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)
KustantajaIEEE
ISBN (elektroninen)978-1-5090-6113-6
DOI - pysyväislinkit
TilaJulkaistu - 2016
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaIEEE International Conference on Electronics, Circuits and Systems -
Kesto: 31 joulukuuta 1899 → …

Conference

ConferenceIEEE International Conference on Electronics, Circuits and Systems
Ajanjakso31/12/99 → …

Tiivistelmä

This paper proposes a customized C programmable processor design to implement the propabilistic binaural speaker localization algorithm that fulfills the challenging requirements placed by the usage context. When compared to a VLIW-based processor design with similar basic computational resources and no special instructions, the proposed processor reaches a 151× speed-up. For a 28nm standard CMOS technology, power consumption of 12 mW (at 50 MHz) and silicon area of 0.3 mm2 is estimated. This is the first publication of a realistic programmable processing architecture for the probabilistic binaural speaker localization or a comparably complex algorithm for hearing aid devices.

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