Design and Silicon Area Optimization of Time-Domain GNSS Receiver Baseband Architectures
|Kustantaja||Tampere University of Technology|
|Tila||Julkaistu - 26 lokakuuta 2018|
|Nimi||Tampere University of Technology. Publication|
This thesis introduces a high level gate count estimation method that provides good accuracy without requiring the hardware being fully speciﬁed. It is based on developing hierarchical models, which are parameterizable, while requiring minimal amount of information about the silicon technology used for the implementation. The average accuracy has been shown to be 4%.
Three time-domain, real-time GNSS receiver baseband architectures are described with a discussion about various optimization methods for eﬃcient implementation: the correlator, the matched ﬁlter, and the group correlator, which is a new architecture combining some of the features of the two ﬁrst ones.
Four use cases are deﬁned for diﬀerent GNSS operating modes: Acquisition, tracking, assisted GNSS, and the combination of the ﬁrst three modes. A comparison is made for receiver basebands including all necessary blocks for full functionality to ﬁnd out which of the three architectures provides the most silicon area eﬃcient implementation.
It is shown that the correlator oﬀers good ﬂexibility, but yields the highest silicon area for acquisition use cases. The matched ﬁlter is best suited for the acquisition, but has large overhead when it comes to tracking the signals. The group correlator oﬀers a reasonably good ﬂexibility and area eﬃciency in all use cases.
The main contributions of the thesis are: Development of domain speciﬁc optimizations for GNSS receivers and an accurate gate count estimation method, which are applied for a quantitative comparison of diﬀerent GNSS receiver architectures. The results show that no single architecture excels in all cases, and the best choice depends on the actual use case.