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Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs

Tutkimustuotosvertaisarvioitu

Standard

Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs. / Boutellier, J.; Nyländen, T.

julkaisussa: Journal of Signal Processing Systems, Vuosikerta 89, Nro 3, 2017, s. 469–478.

Tutkimustuotosvertaisarvioitu

Harvard

Boutellier, J & Nyländen, T 2017, 'Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs', Journal of Signal Processing Systems, Vuosikerta. 89, Nro 3, Sivut 469–478. https://doi.org/10.1007/s11265-017-1260-8

APA

Boutellier, J., & Nyländen, T. (2017). Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs. Journal of Signal Processing Systems, 89(3), 469–478. https://doi.org/10.1007/s11265-017-1260-8

Vancouver

Boutellier J, Nyländen T. Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs. Journal of Signal Processing Systems. 2017;89(3):469–478. https://doi.org/10.1007/s11265-017-1260-8

Author

Boutellier, J. ; Nyländen, T. / Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs. Julkaisussa: Journal of Signal Processing Systems. 2017 ; Vuosikerta 89, Nro 3. Sivut 469–478.

Bibtex - Lataa

@article{c924f7be59cb40ba98d739afe0576b05,
title = "Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs",
abstract = "Dataflow programming has received increasing attention in the age of multicore and heterogeneous computing. Modular and concurrent dataflow program descriptions enable highly automated approaches for design space exploration, optimization and deployment of applications. A great advance in dataflow programming has been the recent introduction of the RVC-CAL language. Having been standardized by the ISO, the RVC-CAL dataflow language provides a solid basis for the development of tools, design methodologies and design flows. This paper proposes a novel design flow for mapping RVC-CAL dataflow programs to parallel and heterogeneous execution platforms. Through the proposed design flow the programmer can describe an application in the RVC-CAL language and map it to multi- and many-core platforms, as well as GPUs, for efficient execution. The functionality and efficiency of the proposed approach is demonstrated by a parallel implementation of a video processing application and a run-time reconfigurable filter for telecommunications. Experiments are performed on GPU and multicore platforms with up to 16 cores, and the results show that for high-performance applications the proposed design flow provides up to 4 × higher throughput than the state-of-the-art approach in multicore execution of RVC-CAL programs.",
keywords = "Dataflow computing, Design automation, Parallel processing, Signal processing",
author = "J. Boutellier and T. Nyl{\"a}nden",
year = "2017",
doi = "10.1007/s11265-017-1260-8",
language = "English",
volume = "89",
pages = "469–478",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer Verlag",
number = "3",

}

RIS (suitable for import to EndNote) - Lataa

TY - JOUR

T1 - Design Flow for GPU and Multicore Execution of Dynamic Dataflow Programs

AU - Boutellier, J.

AU - Nyländen, T.

PY - 2017

Y1 - 2017

N2 - Dataflow programming has received increasing attention in the age of multicore and heterogeneous computing. Modular and concurrent dataflow program descriptions enable highly automated approaches for design space exploration, optimization and deployment of applications. A great advance in dataflow programming has been the recent introduction of the RVC-CAL language. Having been standardized by the ISO, the RVC-CAL dataflow language provides a solid basis for the development of tools, design methodologies and design flows. This paper proposes a novel design flow for mapping RVC-CAL dataflow programs to parallel and heterogeneous execution platforms. Through the proposed design flow the programmer can describe an application in the RVC-CAL language and map it to multi- and many-core platforms, as well as GPUs, for efficient execution. The functionality and efficiency of the proposed approach is demonstrated by a parallel implementation of a video processing application and a run-time reconfigurable filter for telecommunications. Experiments are performed on GPU and multicore platforms with up to 16 cores, and the results show that for high-performance applications the proposed design flow provides up to 4 × higher throughput than the state-of-the-art approach in multicore execution of RVC-CAL programs.

AB - Dataflow programming has received increasing attention in the age of multicore and heterogeneous computing. Modular and concurrent dataflow program descriptions enable highly automated approaches for design space exploration, optimization and deployment of applications. A great advance in dataflow programming has been the recent introduction of the RVC-CAL language. Having been standardized by the ISO, the RVC-CAL dataflow language provides a solid basis for the development of tools, design methodologies and design flows. This paper proposes a novel design flow for mapping RVC-CAL dataflow programs to parallel and heterogeneous execution platforms. Through the proposed design flow the programmer can describe an application in the RVC-CAL language and map it to multi- and many-core platforms, as well as GPUs, for efficient execution. The functionality and efficiency of the proposed approach is demonstrated by a parallel implementation of a video processing application and a run-time reconfigurable filter for telecommunications. Experiments are performed on GPU and multicore platforms with up to 16 cores, and the results show that for high-performance applications the proposed design flow provides up to 4 × higher throughput than the state-of-the-art approach in multicore execution of RVC-CAL programs.

KW - Dataflow computing

KW - Design automation

KW - Parallel processing

KW - Signal processing

U2 - 10.1007/s11265-017-1260-8

DO - 10.1007/s11265-017-1260-8

M3 - Article

VL - 89

SP - 469

EP - 478

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 3

ER -