Design of Intellectual Property-Based Hardware Blocks Integrable with Embedded RISC Processors
|Kustantaja||Tampere University of Technology|
|Tila||Julkaistu - 22 syyskuuta 2017|
|Nimi||Tampere University of Technology. Publication|
Another intention of this work is to prepare a reconﬁgurable platform to send and receive data packets of the next generation wireless communications. Hence, we will further discuss a recently emerged wireless modulation technique known as Non-Contiguous Orthogonal Frequency Division Multiplexing (NC-OFDM), a promising technique to alleviate spectrum scarcity problem. However, one of the primary concerns in such systems is the synchronization. To that end, we developed a reconﬁgurable hardware component to perform as a synchronizer. The developed module exploits Partial Reconﬁguration (PR) feature in order to reconﬁgure itself. Eventually, we will come up with several architectural choices for systems with different limiting factors such as power consumption, operating frequency, and silicon area. The synchronizer can be loosely-coupled via one of the available co-processor slots of the target processor, the COFFEE RISC core.
In addition, we are willing to improve the versatility of the COFFEE core even in industrial use cases. Hence, we developed a reconﬁgurable hardware component capable of operating in the Controller Area Network (CAN) protocol. In the ﬁrst step of this implementation, we mainly concentrate on receiving, decoding, and extracting the data segment of a CAN-based packet. Moreover, this hardware block can reconﬁgure itself on-the-ﬂy to operate on different data frames. More details regarding hardware implementation issues, as well as post synthesis results are also presented. The CAN module is loosely-coupled with the COFFEE RISC processor through one of the available co-processor blocks