Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications
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Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications. / Multanen, Joonas; Kultala, Heikki; Tervo, Kati; Jääskeläinen, Pekka.
julkaisussa: Journal of Signal Processing Systems, 26.07.2020.Tutkimustuotos › › vertaisarvioitu
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TY - JOUR
T1 - Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications
AU - Multanen, Joonas
AU - Kultala, Heikki
AU - Tervo, Kati
AU - Jääskeläinen, Pekka
N1 - INT=comp,"Tervo, Kati"
PY - 2020/7/26
Y1 - 2020/7/26
N2 - Advanced Internet-of-Things applications require control-oriented codes to be executed with low latency for fast responsivity while their advanced signal processing and decision making tasks require computational capabilities. For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2× improvement, while simultaneously achieving a 14% improvement in system energy-delay product.
AB - Advanced Internet-of-Things applications require control-oriented codes to be executed with low latency for fast responsivity while their advanced signal processing and decision making tasks require computational capabilities. For this context, we propose three multi-issue core designs featuring an exposed datapath architecture with high performance, while retaining energy-efficiency. These features are achieved with exploitation of instruction-level parallelism, fast branching and the use of an instruction register file. With benchmarks in control-flow and signal processing application domains we measured in the best case 64% reduced energy consumption compared to a state-of-the-art RISC core, while consuming less silicon area. A high-performance design point reaches nearly 2.6 GHz operating frequency in the best case, over 2× improvement, while simultaneously achieving a 14% improvement in system energy-delay product.
U2 - 10.1007/s11265-020-01578-3
DO - 10.1007/s11265-020-01578-3
M3 - Article
JO - Journal of Signal Processing Systems
JF - Journal of Signal Processing Systems
SN - 1939-8018
ER -