TUTCRIS - Tampereen teknillinen yliopisto

TUTCRIS

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

Tutkimustuotosvertaisarvioitu

Yksityiskohdat

AlkuperäiskieliEnglanti
OtsikkoProceedings of SAMOS XIX: Embedded Computer Systems: Architectures, Modeling, and Simulation
KustantajaSpringer
Sivut3-17
ISBN (painettu)9783030275617
DOI - pysyväislinkit
TilaJulkaistu - heinäkuuta 2019
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation - Samos, Kreikka
Kesto: 7 heinäkuuta 201911 heinäkuuta 2019

Julkaisusarja

NimiLecture Notes in Computer Science
Vuosikerta11733
ISSN (painettu)0302-9743
ISSN (elektroninen)1611-3349

Conference

ConferenceInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation
MaaKreikka
KaupunkiSamos
Ajanjakso7/07/1911/07/19

Tiivistelmä

Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology nodes imply high gate propagation delays, drastically reducing the system’s performance. When reducing area costs and power consumption, the actual processor architecture becomes a major design point. Depending on the application characteristics (i.e., inherent data parallelisms, type of arithmetic,..), several parameters like data path width, instruction execution paradigm, or other architectural design mechanisms have to be considered. This paper presents a design space exploration of five different architectures implemented for a 0.18µm SOI CMOS technology for high temperature using an exemplary case study from the fields of communication, i.e., Reed-Solomon encoder. For this algorithm, an application-specific configuration of a transport-triggered architecture has 37.70x of the performance of a standard 8-bit microcontroller while the silicon area is increased by 4.10x.

Julkaisufoorumi-taso