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High-level parameterizable area estimation modeling for ASIC designs

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High-level parameterizable area estimation modeling for ASIC designs. / Eerola, Ville; Nurmi, Jari.

julkaisussa: Integration: the VLSI Journal, Vuosikerta 47, Nro 4, 2014, s. 461-475.

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Eerola, V & Nurmi, J 2014, 'High-level parameterizable area estimation modeling for ASIC designs', Integration: the VLSI Journal, Vuosikerta. 47, Nro 4, Sivut 461-475. https://doi.org/10.1016/j.vlsi.2014.01.002

APA

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Author

Eerola, Ville ; Nurmi, Jari. / High-level parameterizable area estimation modeling for ASIC designs. Julkaisussa: Integration: the VLSI Journal. 2014 ; Vuosikerta 47, Nro 4. Sivut 461-475.

Bibtex - Lataa

@article{efc9d8aa03a3479580e2e79572ea117b,
title = "High-level parameterizable area estimation modeling for ASIC designs",
author = "Ville Eerola and Jari Nurmi",
note = "Contribution: organisation=elt,FACT1=1<br/>Portfolio EDEND: 2014-08-28<br/>Publisher name: Elsevier",
year = "2014",
doi = "10.1016/j.vlsi.2014.01.002",
language = "English",
volume = "47",
pages = "461--475",
journal = "Integration: the VLSI Journal",
issn = "0167-9260",
publisher = "Elsevier",
number = "4",

}

RIS (suitable for import to EndNote) - Lataa

TY - JOUR

T1 - High-level parameterizable area estimation modeling for ASIC designs

AU - Eerola, Ville

AU - Nurmi, Jari

N1 - Contribution: organisation=elt,FACT1=1<br/>Portfolio EDEND: 2014-08-28<br/>Publisher name: Elsevier

PY - 2014

Y1 - 2014

U2 - 10.1016/j.vlsi.2014.01.002

DO - 10.1016/j.vlsi.2014.01.002

M3 - Article

VL - 47

SP - 461

EP - 475

JO - Integration: the VLSI Journal

JF - Integration: the VLSI Journal

SN - 0167-9260

IS - 4

ER -