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Intra-CPU traffic estimation and implications on networks-on-chip research

Tutkimustuotosvertaisarvioitu

Yksityiskohdat

AlkuperäiskieliEnglanti
OtsikkoInternet of Things, Smart Spaces, and Next Generation Networks and Systems - 16th International Conference, NEW2AN 2016 and 9th Conference, ruSMART 2016, Proceedings
KustantajaSpringer International Publishing AG
Sivut453-464
Sivumäärä12
ISBN (painettu)9783319463001
DOI - pysyväislinkit
TilaJulkaistu - 20 syyskuuta 2016
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaInternational Conference on Next Generation Wired/Wireless Advanced Networks and Systems -
Kesto: 1 tammikuuta 1900 → …

Julkaisusarja

NimiLecture Notes in Computer Science
Vuosikerta9870
ISSN (painettu)0302-9743
ISSN (elektroninen)1611-3349

Conference

ConferenceInternational Conference on Next Generation Wired/Wireless Advanced Networks and Systems
Ajanjakso1/01/00 → …

Tiivistelmä

General purpose networks-on-chip (GP-NoC) are expected to feature tens or even hundreds of computational elements with complex communications infrastructure binding them into a connected network to achieve memory synchronization. The experience accumulated over the years in network design suggests that the knowledge of the traffic nature is mandatory for successful design of a networking technology. In this paper, based on the Intel CPU family, we describe traffic estimation techniques for modern multi-core GP-CPUs, discuss the traffic modeling procedure and highlight the implications of the traffic structure for GP-NoC research. The most important observation is that the traffic at internal interfaces appears to be random for external observer and has clearly identifiable batch structure.

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