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Low-Power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

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Yksityiskohdat

AlkuperäiskieliEnglanti
Otsikko2019 IEEE International Conference on Acoustics, Speech and Signal Processing Proceedings
KustantajaIEEE
ISBN (elektroninen)978-1-4799-8131-1
DOI - pysyväislinkit
TilaJulkaistu - 17 huhtikuuta 2019
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaIEEE International Conference on Acoustics, Speech and Signal Processing - Brighton, Iso-Britannia
Kesto: 12 toukokuuta 201917 toukokuuta 2019

Conference

ConferenceIEEE International Conference on Acoustics, Speech and Signal Processing
MaaIso-Britannia
KaupunkiBrighton
Ajanjakso12/05/1917/05/19

Tiivistelmä

This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.

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