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Models of architecture: Reproducible efficiency evaluation for signal processing systems

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Standard

Models of architecture : Reproducible efficiency evaluation for signal processing systems. / Pelcat, Maxime; Desnos, Karol; Maggiani, Luca; Liu, Yanzhou; Heulot, Julien; Nezan, Jean François; Bhattacharyya, Shuvra S.

IEEE International Workshop on Signal Processing Systems, SiPS 2016. IEEE, 2016. s. 121-126 7780083 (IEEE International Workshop on Signal Processing Systems).

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Harvard

Pelcat, M, Desnos, K, Maggiani, L, Liu, Y, Heulot, J, Nezan, JF & Bhattacharyya, SS 2016, Models of architecture: Reproducible efficiency evaluation for signal processing systems. julkaisussa IEEE International Workshop on Signal Processing Systems, SiPS 2016., 7780083, IEEE International Workshop on Signal Processing Systems, IEEE, Sivut 121-126, 1/01/00. https://doi.org/10.1109/SiPS.2016.29

APA

Pelcat, M., Desnos, K., Maggiani, L., Liu, Y., Heulot, J., Nezan, J. F., & Bhattacharyya, S. S. (2016). Models of architecture: Reproducible efficiency evaluation for signal processing systems. teoksessa IEEE International Workshop on Signal Processing Systems, SiPS 2016 (Sivut 121-126). [7780083] (IEEE International Workshop on Signal Processing Systems). IEEE. https://doi.org/10.1109/SiPS.2016.29

Vancouver

Pelcat M, Desnos K, Maggiani L, Liu Y, Heulot J, Nezan JF et al. Models of architecture: Reproducible efficiency evaluation for signal processing systems. julkaisussa IEEE International Workshop on Signal Processing Systems, SiPS 2016. IEEE. 2016. s. 121-126. 7780083. (IEEE International Workshop on Signal Processing Systems). https://doi.org/10.1109/SiPS.2016.29

Author

Pelcat, Maxime ; Desnos, Karol ; Maggiani, Luca ; Liu, Yanzhou ; Heulot, Julien ; Nezan, Jean François ; Bhattacharyya, Shuvra S. / Models of architecture : Reproducible efficiency evaluation for signal processing systems. IEEE International Workshop on Signal Processing Systems, SiPS 2016. IEEE, 2016. Sivut 121-126 (IEEE International Workshop on Signal Processing Systems).

Bibtex - Lataa

@inproceedings{730a0f326b004521b6179a66d8eac3fb,
title = "Models of architecture: Reproducible efficiency evaluation for signal processing systems",
abstract = "The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communicationrelated part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.",
author = "Maxime Pelcat and Karol Desnos and Luca Maggiani and Yanzhou Liu and Julien Heulot and Nezan, {Jean Fran{\cc}ois} and Bhattacharyya, {Shuvra S.}",
year = "2016",
month = "12",
day = "9",
doi = "10.1109/SiPS.2016.29",
language = "English",
series = "IEEE International Workshop on Signal Processing Systems",
publisher = "IEEE",
pages = "121--126",
booktitle = "IEEE International Workshop on Signal Processing Systems, SiPS 2016",

}

RIS (suitable for import to EndNote) - Lataa

TY - GEN

T1 - Models of architecture

T2 - Reproducible efficiency evaluation for signal processing systems

AU - Pelcat, Maxime

AU - Desnos, Karol

AU - Maggiani, Luca

AU - Liu, Yanzhou

AU - Heulot, Julien

AU - Nezan, Jean François

AU - Bhattacharyya, Shuvra S.

PY - 2016/12/9

Y1 - 2016/12/9

N2 - The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communicationrelated part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.

AB - The current trend in high performance and embedded signal processing consists of designing increasingly complex heterogeneous hardware architectures with non-uniform communication resources. In order to take hardware and software design decisions, early evaluations of the system non-functional properties are needed. These evaluations of system efficiency require high-level information on both the algorithms and the architecture. In this paper, we define the notion of Model of Architecture (MoA) and study the combination of a Model of Computation (MoC) and an MoA to provide a design space exploration environment for the study of the algorithmic and architectural choices. A cost is computed from the mapping of an application, represented by a model conforming a MoC onto an architecture represented by a model conforming an MoA. The cost is composed of a processing-related part and a communicationrelated part. It is an abstract scalar value to be minimized and can represent any non-functional requirement of a system such as memory, energy, throughput or latency.

U2 - 10.1109/SiPS.2016.29

DO - 10.1109/SiPS.2016.29

M3 - Conference contribution

T3 - IEEE International Workshop on Signal Processing Systems

SP - 121

EP - 126

BT - IEEE International Workshop on Signal Processing Systems, SiPS 2016

PB - IEEE

ER -