Multidimensional dataflow graph modeling and mapping for efficient GPU implementation
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Yksityiskohdat
| Alkuperäiskieli | Englanti |
|---|---|
| Otsikko | Proceedings - 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 |
| Sivut | 300-305 |
| Sivumäärä | 6 |
| DOI - pysyväislinkit | |
| Tila | Julkaistu - 2012 |
| OKM-julkaisutyyppi | A4 Artikkeli konferenssijulkaisussa |
| Tapahtuma | 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 - Quebec City, QC, Kanada Kesto: 17 lokakuuta 2012 → 19 lokakuuta 2012 |
Conference
| Conference | 2012 IEEE Workshop on Signal Processing Systems, SiPS 2012 |
|---|---|
| Maa | Kanada |
| Kaupunki | Quebec City, QC |
| Ajanjakso | 17/10/12 → 19/10/12 |
Tiivistelmä
Multidimensional synchronous dataflow (MDSDF) provides an effective model of computation for a variety of multidimensional DSP systems that have static dataflow structures. In this paper, we develop new methods for optimized implementation of MDSDF graphs on embedded platforms that employ multiple levels of parallelism to enhance performance at different levels of granularity. Our approach allows designers to systematically represent and transform multi-level parallelism specifications from a common, MDSDF-based application level model. We demonstrate our methods with a case study of image histogram implementation on a graphics processing unit (GPU). Experimental results from this study show that our approach can be used to derive fast GPU implementations, and enhance trade-off analysis during design space exploration.