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Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters

Tutkimustuotosvertaisarvioitu

Standard

Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters. / Palomäki, H.; Saramäki, T.; Tenhunen, H.

Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz. New York : IEEE Press, 1988. s. 523-534.

Tutkimustuotosvertaisarvioitu

Harvard

Palomäki, H, Saramäki, T & Tenhunen, H 1988, Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters. julkaisussa Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz. IEEE Press, New York, Sivut 523-534.

APA

Palomäki, H., Saramäki, T., & Tenhunen, H. (1988). Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters. teoksessa Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz (Sivut 523-534). New York: IEEE Press.

Vancouver

Palomäki H, Saramäki T, Tenhunen H. Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters. julkaisussa Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz. New York: IEEE Press. 1988. s. 523-534

Author

Palomäki, H. ; Saramäki, T. ; Tenhunen, H. / Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters. Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz. New York : IEEE Press, 1988. Sivut 523-534

Bibtex - Lataa

@inproceedings{68c35280793b4f58ab161c845141768e,
title = "Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters",
author = "H. Palom{\"a}ki and T. Saram{\"a}ki and H. Tenhunen",
note = "Contribution: organisation=sgn,FACT1=1",
year = "1988",
language = "English",
pages = "523--534",
booktitle = "Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz",
publisher = "IEEE Press",

}

RIS (suitable for import to EndNote) - Lataa

TY - GEN

T1 - Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters

AU - Palomäki, H.

AU - Saramäki, T.

AU - Tenhunen, H.

N1 - Contribution: organisation=sgn,FACT1=1

PY - 1988

Y1 - 1988

M3 - Conference contribution

SP - 523

EP - 534

BT - Presented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz

PB - IEEE Press

CY - New York

ER -