TUTCRIS - Tampereen teknillinen yliopisto


Optimization of ESD Protection Methods in Electronics Assembly Based on Process and Product Specific Risks



KustantajaTampere University of Technology
ISBN (elektroninen)978-952-15-3870-4
ISBN (painettu)978-952-15-3858-2
TilaJulkaistu - 9 joulukuuta 2016
OKM-julkaisutyyppiG5 Artikkeliväitöskirja


NimiTampere University of Technology. Publication
ISSN (painettu)1459-2045


The last 40 years has seen significant development in electrical component and system technologies. However, advances with semiconductor technologies, cost optimizations, and die area shrinking have made electronics more sensitive to excess electrical stress and electromagnetic disturbances. In this dissertation work, one of these stress scenarios is studied: electrostatic discharge (ESD) risks in the electronics assembly process environment. In the assembly process, single electrical components, circuit boards, and different subassemblies are assembled together, tested, and programmed to complete fully functional electrical products.

A noncontrolled electronics assembly environment produces unpredictable ESD risks and causes yield losses. Therefore, it is necessary to protect electronics against ESD during handling and manufacturing. This is accomplished with the aid of an electrostatic protected area (EPA) and an ESD control program plan, which are typically built according to IEC61340-5-1-2007 and ANSI S20.20-2014 standards. These two standards define how to design, establish, implement, and maintain the program with administrative and technical requirements. Here, a 100 V human body model (HBM) limit is currently used as the base for building EPAs and ESD control programs. However, current ESD control programs are not always able to prevent ESD damages in EPA. On top of actual ESD events, there can be electromagnetic interference (EMI) initiated product and equipment disturbances in well-built EPAs.

In this research work, the main focus is on additional ESD control methods that go beyond the specifications and requirements of the IEC61340-5-1 and ANSI/ESD S20.20 standards. The objective is to optimize ESD protection methods based on real ESD risk scenarios found during PCB assembly, testing, handling, and during system final assembly to achieve close to zero-failure level. At the same time, the objective is to optimize ESD control-related costs in the process area.

Based on the research, the focus of the additional ESD and EMI control methods should be with final assembly, programming, and testing process phases where about 90% observed failure and disturbance cases have occurred. Therefore, in an improved ESD control program, EMI control, controlling product part and cable charging are added into the program, together with groundings and other basic controlled EPA items. The charging of product parts should be monitored with potential, discharge current and charge meters, and that data should be used together with process analysis to detect all known ESD risk scenarios. The sensitivity of subassemblies should be tested, for example, by using a charged board event (CBE), field collapse event (FCE), and cable discharge event (CDE) methods that simulate real world ESD scenarios found in the process area. This gives more accurate data for risk assessments than an electrical-component-specific HBM or charged device model (CDM) qualification data.

The proposed additional control methods were implemented in more than 10 large electronics assembly facilities, resulting in a significant reduction in ESD-related failures and disturbance-related process yield challenges. Therefore, as a future work, product and process specific ESD and EMI risk should be emphasized in ESDcontrol-related trainings, standards, standard practices, and technical reports.

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