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Parallel processing intensive digital front-end for IEEE 802.11ac receiver

Tutkimustuotosvertaisarvioitu

Standard

Parallel processing intensive digital front-end for IEEE 802.11ac receiver. / Aghababaeetafreshi, Mona; Yli-Kaakinen, Juha; Levanen, Toni; Korhonen, Ville; Jääskeläinen, Pekka; Renfors, Markku; Valkama, Mikko; Takala, Jarmo.

2015 49th Asilomar Conference on Signals, Systems and Computers. IEEE, 2016. s. 1619-1626 .

Tutkimustuotosvertaisarvioitu

Harvard

Aghababaeetafreshi, M, Yli-Kaakinen, J, Levanen, T, Korhonen, V, Jääskeläinen, P, Renfors, M, Valkama, M & Takala, J 2016, Parallel processing intensive digital front-end for IEEE 802.11ac receiver. julkaisussa 2015 49th Asilomar Conference on Signals, Systems and Computers. IEEE, Sivut 1619-1626 , Pacific Grove, Yhdysvallat, 8/11/15. https://doi.org/10.1109/ACSSC.2015.7421422

APA

Aghababaeetafreshi, M., Yli-Kaakinen, J., Levanen, T., Korhonen, V., Jääskeläinen, P., Renfors, M., ... Takala, J. (2016). Parallel processing intensive digital front-end for IEEE 802.11ac receiver. teoksessa 2015 49th Asilomar Conference on Signals, Systems and Computers (Sivut 1619-1626 ). IEEE. https://doi.org/10.1109/ACSSC.2015.7421422

Vancouver

Aghababaeetafreshi M, Yli-Kaakinen J, Levanen T, Korhonen V, Jääskeläinen P, Renfors M et al. Parallel processing intensive digital front-end for IEEE 802.11ac receiver. julkaisussa 2015 49th Asilomar Conference on Signals, Systems and Computers. IEEE. 2016. s. 1619-1626 https://doi.org/10.1109/ACSSC.2015.7421422

Author

Aghababaeetafreshi, Mona ; Yli-Kaakinen, Juha ; Levanen, Toni ; Korhonen, Ville ; Jääskeläinen, Pekka ; Renfors, Markku ; Valkama, Mikko ; Takala, Jarmo. / Parallel processing intensive digital front-end for IEEE 802.11ac receiver. 2015 49th Asilomar Conference on Signals, Systems and Computers. IEEE, 2016. Sivut 1619-1626

Bibtex - Lataa

@inproceedings{a6840ebc219a4452954e23b1b07a624f,
title = "Parallel processing intensive digital front-end for IEEE 802.11ac receiver",
abstract = "Modern computing platforms offer increasing levels of parallelism for fast execution of different signal processing tasks. In this paper, we develop and elaborate on a digital front-end concept for an IEEE 802.11ac receiver with 80 MHz bandwidth where parallel processing is adopted in multiple ways. First, the inherent structure of the 802.11ac waveform is utilized such that it is divided, through time-domain digital filtering and decimation, to two parallel 40 MHz signals that can be processed further in parallel using smaller-size FFTs and, e.g, legacy 802.11n digital receiver chains. This filtering task is very challenging, as the latency and the cyclic prefix budget of the receiver cannot be compromised, and because the number of unused subcarriers in the middle of the 80 MHz signal is only three, thus necessitating very narrow transition bandwidth in the deployed filters. Both linear and circular filtering based multirate channelization architectures are developed and reported, together with the corresponding filter coefficient optimization. Also, full radio link performance simulations with commonly adopted indoor WiFi channel profiles are provided, verifying that the channelization does not degrade the overall link performance. Then, both C and OpenCL software implementations of the processing are developed and simulated for comparison purposes on an Intel CPU, to demonstrate that the parallelism provided by the OpenCL will result in substantially faster realization. Furthermore, we provide complete software implementation results in terms of time, number of clock cycles, power, and energy consumption on the ARM Mali GPU with half precision floating-point arithmetic along with the ARM Cortex A7 CPU.",
author = "Mona Aghababaeetafreshi and Juha Yli-Kaakinen and Toni Levanen and Ville Korhonen and Pekka J{\"a}{\"a}skel{\"a}inen and Markku Renfors and Mikko Valkama and Jarmo Takala",
year = "2016",
doi = "10.1109/ACSSC.2015.7421422",
language = "English",
isbn = "978-1-4673-8574-9",
publisher = "IEEE",
pages = "1619--1626",
booktitle = "2015 49th Asilomar Conference on Signals, Systems and Computers",

}

RIS (suitable for import to EndNote) - Lataa

TY - GEN

T1 - Parallel processing intensive digital front-end for IEEE 802.11ac receiver

AU - Aghababaeetafreshi, Mona

AU - Yli-Kaakinen, Juha

AU - Levanen, Toni

AU - Korhonen, Ville

AU - Jääskeläinen, Pekka

AU - Renfors, Markku

AU - Valkama, Mikko

AU - Takala, Jarmo

PY - 2016

Y1 - 2016

N2 - Modern computing platforms offer increasing levels of parallelism for fast execution of different signal processing tasks. In this paper, we develop and elaborate on a digital front-end concept for an IEEE 802.11ac receiver with 80 MHz bandwidth where parallel processing is adopted in multiple ways. First, the inherent structure of the 802.11ac waveform is utilized such that it is divided, through time-domain digital filtering and decimation, to two parallel 40 MHz signals that can be processed further in parallel using smaller-size FFTs and, e.g, legacy 802.11n digital receiver chains. This filtering task is very challenging, as the latency and the cyclic prefix budget of the receiver cannot be compromised, and because the number of unused subcarriers in the middle of the 80 MHz signal is only three, thus necessitating very narrow transition bandwidth in the deployed filters. Both linear and circular filtering based multirate channelization architectures are developed and reported, together with the corresponding filter coefficient optimization. Also, full radio link performance simulations with commonly adopted indoor WiFi channel profiles are provided, verifying that the channelization does not degrade the overall link performance. Then, both C and OpenCL software implementations of the processing are developed and simulated for comparison purposes on an Intel CPU, to demonstrate that the parallelism provided by the OpenCL will result in substantially faster realization. Furthermore, we provide complete software implementation results in terms of time, number of clock cycles, power, and energy consumption on the ARM Mali GPU with half precision floating-point arithmetic along with the ARM Cortex A7 CPU.

AB - Modern computing platforms offer increasing levels of parallelism for fast execution of different signal processing tasks. In this paper, we develop and elaborate on a digital front-end concept for an IEEE 802.11ac receiver with 80 MHz bandwidth where parallel processing is adopted in multiple ways. First, the inherent structure of the 802.11ac waveform is utilized such that it is divided, through time-domain digital filtering and decimation, to two parallel 40 MHz signals that can be processed further in parallel using smaller-size FFTs and, e.g, legacy 802.11n digital receiver chains. This filtering task is very challenging, as the latency and the cyclic prefix budget of the receiver cannot be compromised, and because the number of unused subcarriers in the middle of the 80 MHz signal is only three, thus necessitating very narrow transition bandwidth in the deployed filters. Both linear and circular filtering based multirate channelization architectures are developed and reported, together with the corresponding filter coefficient optimization. Also, full radio link performance simulations with commonly adopted indoor WiFi channel profiles are provided, verifying that the channelization does not degrade the overall link performance. Then, both C and OpenCL software implementations of the processing are developed and simulated for comparison purposes on an Intel CPU, to demonstrate that the parallelism provided by the OpenCL will result in substantially faster realization. Furthermore, we provide complete software implementation results in terms of time, number of clock cycles, power, and energy consumption on the ARM Mali GPU with half precision floating-point arithmetic along with the ARM Cortex A7 CPU.

UR - http://www.asilomarsscconf.org/

U2 - 10.1109/ACSSC.2015.7421422

DO - 10.1109/ACSSC.2015.7421422

M3 - Conference contribution

SN - 978-1-4673-8574-9

SP - 1619

EP - 1626

BT - 2015 49th Asilomar Conference on Signals, Systems and Computers

PB - IEEE

ER -