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Performance evaluation of a flow control algorithm for network-on-chip

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Yksityiskohdat

AlkuperäiskieliEnglanti
OtsikkoProceedings of the 2012 International Conference on High Performance Computing and Simulation, HPCS 2012
Sivut281-287
Sivumäärä7
DOI - pysyväislinkit
TilaJulkaistu - 2012
Julkaistu ulkoisestiKyllä
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaINTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND SIMULATION -
Kesto: 1 tammikuuta 1900 → …

Conference

ConferenceINTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND SIMULATION
Ajanjakso1/01/00 → …

Tiivistelmä

Network-on-chip (NoC) has been proposed for SoC (System-on-Chip) as an alternative to on-chip bus-based interconnects to achieve better performance and lower energy consumption. Several approaches have been proposed to deal with NoCs design and can be classified into two main categories, design-time approaches and run-time approaches. Design-time approaches are generally tailored for an application domain or a specific application by providing a customized NoC. All parameters, such as routing and switching schemes, are defined at design time. Run-time approaches, however, provide techniques that allow a NoC to continuously adapt its structure and its behavior (i.e., at runtime). In this paper, performance evaluation of a flow control algorithm for congestion avoidance in NoCs is presented. This algorithm allows NoC elements to dynamically adjust their inflow by using a feedback control-based mechanism. Analytical and simulation results are reported to show the viability of this mechanism for congestion avoidance in NoCs.

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