TUTCRIS - Tampereen teknillinen yliopisto


Scalable multiprocessor system-on-chip architecture design on FPGA



KustantajaTampere University of Technology
ISBN (elektroninen)978-952-15-2122-5
ISBN (painettu)978-952-15-2102-7
TilaJulkaistu - 30 tammikuuta 2009
OKM-julkaisutyyppiG5 Artikkeliväitöskirja


NimiTampere University of Technology. Publication
KustantajaTampere University of Technology
ISSN (painettu)1459-2045


Most system-on-chip architectures have been targeted for ASICs, but the capacity of FPGAs has increased to allow multi-processor system-on-chip implementations. FPGAs feature differently constrained environment with respect to ASIC and implementations that work well in ASIC may not suit the FPGA. Following this, FPGA-specific architectures are required for efficient resource usage. Furthermore, the re-usability and flexibility of the digital systems needs to be increased in order to keep on pace of the increased functionality and need for increased productivity. The main contribution of this Thesis is FLARE (FLexible multiprocessor Architecture with Rapid Expandability): a modular, scalable multiprocessor system-on-chip architecture targeted for FPGA. The main objective is to increase productivity by allowing the system designer to concentrate fully on system-level issues - such as targeted device, number of processors, and architecture modularity - instead of burdening to e.g. integration details. In addition to design of FLARE, three main subjects of FLARE are considered in more detail. First, studies and development of the interconnection on FPGA are made. Second, thorough measurements with different configurations have been conducted. Finally, supporting tools for FLARE and novel measurement environment has been created. FLARE supports easy component re-use, multiple clock domains with synchronizers, vendor-independent inter-FPGA links, resource management and mutual exclusion of shared components and modularized structure with efficient FPGA resource usage. The studies with real MPEG-4 video encoder show high scalability and simple expandability of FLARE. It has been found out that hierarchical bus structures are best for FPGA. Also, using multiple clock domains is important for modularizing the design but do not yield performance improvement. Unconventional instruction memory sharing of the processors has been studied and found to suit the FPGA significantly better than traditional distributed instruction memory. FLARE allows also to prototype and analyze anticipated future systems even years earlier than enabled by the technology. The results of this Thesis show that, in accordance of the International Technology Roadmap for Semiconductors, FLARE provides even up to 12x-27x productivity improvement over conventional architectures. The productivity improvement requires also a paradigm shift in software design in order to support parallel programs instead of typical sequential ones.


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