SHRIMP: Efficient Instruction Delivery with Domain Wall Memory
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Yksityiskohdat
| Alkuperäiskieli | Englanti |
|---|---|
| Otsikko | International Symposium on Low Power Electronics and Design, ISLPED 2019 |
| Kustantaja | IEEE |
| ISBN (elektroninen) | 9781728129549 |
| DOI - pysyväislinkit | |
| Tila | Julkaistu - elokuuta 2019 |
| OKM-julkaisutyyppi | A4 Artikkeli konferenssijulkaisussa |
| Tapahtuma | IEEE/ACM International Symposium on Low Power Electronics and Design - Lausanne, Sveitsi Kesto: 29 heinäkuuta 2019 → 31 heinäkuuta 2019 |
Julkaisusarja
| Nimi | Edit Proceedings of the International Symposium on Low Power Electronics and Design |
|---|---|
| ISSN (painettu) | 1533-4678 |
Conference
| Conference | IEEE/ACM International Symposium on Low Power Electronics and Design |
|---|---|
| Maa | Sveitsi |
| Kaupunki | Lausanne |
| Ajanjakso | 29/07/19 → 31/07/19 |
Tiivistelmä
Domain Wall Memory (DWM) is a promising emerging memory technology but suffers from the expensive shifts needed to align memory locations with access ports. Previous work on DWM concentrates on data, while, to the best of our knowledge, techniques to specifically target instruction streams have not yet been studied. In this paper, we propose Shift-Reducing Instruction Memory Placement (SHRIMP), the first instruction placement strategy suited for DWM which is accompanied with a supporting instruction fetch and memory architecture. The proposed approach reduces the number of shifts by 40% in the best case with a small memory overhead. In addition, SHRIMP achieves a best case of 23% reduction in total cycle counts.
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