TUTCRIS - Tampereen teknillinen yliopisto

TUTCRIS

Transport Triggered Polar Decoders

Tutkimustuotosvertaisarvioitu

Yksityiskohdat

AlkuperäiskieliEnglanti
Otsikko2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC)
KustantajaIEEE
ISBN (elektroninen)978-1-5386-7048-4
DOI - pysyväislinkit
TilaJulkaistu - 4 joulukuuta 2018
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaInternational Symposium on Turbo Codes & Iterative Information Processing - Hong Kong, Kiina
Kesto: 3 joulukuuta 20187 joulukuuta 2018
http://www.istc2018.org/

Conference

ConferenceInternational Symposium on Turbo Codes & Iterative Information Processing
LyhennettäISTC 2018
MaaKiina
KaupunkiHong Kong
Ajanjakso3/12/187/12/18
www-osoite

Tiivistelmä

In this paper, the first transport triggered architecture (TTA) customized for the decoding of polar codes is proposed. A first version of this programmable processor is optimized for the successive cancellation (SC) decoding of polar codes while a second architecture is further specialized to also support Soft CANcellation (SCAN) decoding. Both architectures were fully validated on FPGA device by prototyping. The first architecture was also synthesized in 28nm ASIC technology. It runs at a frequency of 800 MHz and reaches a throughput of 352 Mbps for a (1024, 512) polar code decoded with the SC algorithm. Compared to previous work, the energy consumption is reduced by one order of magnitude (0.14 nJ / bit) and the throughput is increased fivefold. Compared to an optimized software implementation on a general purpose processor (x86 architecture), the throughput is 37 % higher and the energy consumption is two orders of magnitude lower. TTA can be seen as a way to reduce the gap between programmable and dedicated polar decoders.

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