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Variable Length Instruction Compression on Transport Triggered Architectures

Tutkimustuotos: vertaisarvioituKonferenssiartikkeli

Yksityiskohdat

Julkaisun otsikon käännösVariable Length Instruction Compression on Transport Triggered Architectures
AlkuperäiskieliEnglanti
Otsikko2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XIV, Samos Island, Greece, July 14-17, 2014
KustantajaInstitute of Electrical and Electronics Engineers IEEE
Sivut149-155
Sivumäärä7
ISBN (painettu)978-1-4799-3770-7
TilaJulkaistu - 2014
OKM-julkaisutyyppiA4 Artikkeli konferenssijulkaisussa
TapahtumaINTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION -

Conference

ConferenceINTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION
Ajanjakso1/01/00 → …

Tiivistelmä

The SRAM memories used for embedded micro-processor devices consume a large portion of the system's power. The power dissipation of the instruction memory can be limited by using code compression methods, which may require the use of variable length instruction formats in the processor. The power-efficient design of variable length instruction fetch and decode is challenging for static multiple-issue processors, which aim for low power consumption on embedded platforms. The power saved using compression is easily lost on inefficient processor design. We propose an implementation for instruction template -based compression and two instruction fetch alternatives for variable length instruction encoding on Transport Triggered Architecture, a static multiple-issue exposed data path architecture. The compression approach reaches an average program size reduction of 44% at best. We show that the variable length fetch designs are sufficiently low-power oriented for the system to benefit from the code compression, which reduces the program memory size.

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