VHDL to Modelling Language Translator
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VHDL to Modelling Language Translator. / Nousiainen, J.; Vainio, O.
Proc. on Euro-VHDL 91, -Second European Conference on VHDL Methods, Stockholm, Sweden, 8-11 Sept., 1991. 1991.Tutkimustuotos ›
Harvard
Nousiainen, J & Vainio, O 1991, VHDL to Modelling Language Translator. julkaisussa Proc. on Euro-VHDL 91, -Second European Conference on VHDL Methods, Stockholm, Sweden, 8-11 Sept., 1991.
APA
Nousiainen, J., & Vainio, O. (1991). VHDL to Modelling Language Translator. teoksessa Proc. on Euro-VHDL 91, -Second European Conference on VHDL Methods, Stockholm, Sweden, 8-11 Sept., 1991
Vancouver
Nousiainen J, Vainio O. VHDL to Modelling Language Translator. julkaisussa Proc. on Euro-VHDL 91, -Second European Conference on VHDL Methods, Stockholm, Sweden, 8-11 Sept., 1991. 1991
Author
Bibtex - Lataa
@inproceedings{4d161e6588284e549ab32a351b97f437,
title = "VHDL to Modelling Language Translator",
author = "J. Nousiainen and O. Vainio",
note = "Contribution: organisation=sgn,FACT1=1",
year = "1991",
language = "English",
booktitle = "Proc. on Euro-VHDL 91, -Second European Conference on VHDL Methods, Stockholm, Sweden, 8-11 Sept., 1991",
}
RIS (suitable for import to EndNote) - Lataa
TY - GEN
T1 - VHDL to Modelling Language Translator
AU - Nousiainen, J.
AU - Vainio, O.
N1 - Contribution: organisation=sgn,FACT1=1
PY - 1991
Y1 - 1991
M3 - Conference contribution
BT - Proc. on Euro-VHDL 91, -Second European Conference on VHDL Methods, Stockholm, Sweden, 8-11 Sept., 1991
ER -